参数资料
型号: M68AW512DL70ZB6F
厂商: STMICROELECTRONICS
元件分类: SRAM
英文描述: 512K X 16 STANDARD SRAM, 70 ns, PBGA48
封装: 8 X 10 MM, 0.75 MM PITCH, ROHS COMPLIANT, TFBGA-48
文件页数: 10/23页
文件大小: 427K
代理商: M68AW512DL70ZB6F
Obsolete
Product(s)
- Obsolete
Product(s)
M68AW512D
18/23
Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms
Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms
Table 9. Low VCC Data Retention Characteristics
Note: 1. All other Inputs at VIH ≥ VCC –0.2V or VIL ≤ 0.2V.
2. Tested initially and after any design or process that may affect these parameters.
tAVAV is Read cycle time.
3. No input may exceed VCC +0.2V.
Symbol
Parameter
Test Condition
Min
Max
Unit
ICCDR
(1)
Supply Current (Data Retention)
VCC = 1.5V, E1 ≥ VCC –0.2V or
E2
≤ 0.2V or UB = LB ≥ VCC –0.2V, f = 0
30
A
tCDR
(1,2)
Chip Deselected to Data
Retention Time
0ns
tR
(2)
Operation Recovery Time
tAVAV
ns
VDR
(1)
Supply Voltage (Data Retention)
E1
≥ VCC –0.2V or E2 ≤ 0.2V or
UB = LB
≥ VCC –0.2V, f = 0
1.5
V
AI05985
DATA RETENTION MODE
tR
3.6V
tCDR
VCC
2.7V
VDR > 1.5V
E1 or UB/LB
E1
≥ VDR – 0.2V or UB = LB ≥ VDR – 0.2V
AI05986c
DATA RETENTION MODE
tR
3.6V
tCDR
VCC
2.7V
VDR > 1.5V
E2
E2 < 0.2V
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