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参数资料
| 型号： | M68AW512DL70ZB6F |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | SRAM |
| 英文描述： | 512K X 16 STANDARD SRAM, 70 ns, PBGA48 |
| 封装： | 8 X 10 MM, 0.75 MM PITCH, ROHS COMPLIANT, TFBGA-48 |
| 文件页数： | 6/23页 |
| 文件大小： | 427K |
| 代理商： | M68AW512DL70ZB6F |
Obsolete
Product(s)
- Obsolete
Product(s)
M68AW512D
14/23
Table 7. Read and Standby Mode AC Characteristics
Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC.
2. At any given temperature and voltage condition, tGHQZ is less than tGLQX, tBHQZ is less than tBLQX and tEHQZ is less than tELQX for
any given device.
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
Symbol
Parameter
M68AW512D
Unit
55
70
tAVAV
Read Cycle Time
Min
55
70
ns
tAVQV
Address Valid to Output Valid
Max
55
70
ns
tAXQX
(1)
Data hold from address change
Min
5
ns
tBHQZ
(2,3,4)
Upper/Lower Byte Enable High to Output Hi-Z
Max
20
25
ns
tBLQV
Upper/Lower Byte Enable Low to Output Valid
Max
55
70
ns
tBLQX
(1)
Upper/Lower Byte Enable Low to Output Transition
Min
5
ns
tEHQZ
(2,3,4)
Chip Enable High to Output Hi-Z
Max
20
25
ns
tELQV
Chip Enable Low to Output Valid
Max
55
70
ns
tELQX
(1)
Chip Enable Low to Output Transition
Min
5
ns
tGHQZ
(2,3,4)
Output Enable High to Output Hi-Z
Max
20
25
ns
tGLQV
Output Enable Low to Output Valid
Max
25
35
ns
tGLQX
(1)
Output Enable Low to Output Transition
Min
5
ns
tPD
Chip Enable or UB/LB High to Power Down
Max
55
70
ns
tPU
Chip Enable or UB/LB Low to Power Up
Min
0
ns
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相关代理商/技术参数 |
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|---|---|
| M68AW512DL70ZB6T | 制造商:STMicroelectronics 功能描述: |
| M68AW512DN55ZB1T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit 512K x16 3.0V Asynchronous SRAM |
| M68AW512DN55ZB6 | 制造商:STMicroelectronics 功能描述: |
| M68AW512DN55ZB6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit 512K x16 3.0V Asynchronous SRAM |
| M68AW512DN70ZB1T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit 512K x16 3.0V Asynchronous SRAM |
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