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参数资料
| 型号： | M68HC11K |
| 厂商： | Motorola, Inc. |
| 元件分类： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件页数： | 28/80页 |
| 文件大小： | 420K |
| 代理商： | M68HC11K |
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MOTOROLA
28
M68HC11 K Series
MC68HC11KTS/D
Bits [7:6] — Not implemented
Always read zero
PGAR[5:0] —Port G Pin Assignment Bits [5:0]
0 = Corresponding port G pin is general-purpose I/O
1 = Corresponding port G pin is address line, XA[18:13]
NOTE
A special case exists for expansion address lines XA[15:13] that overlap the CPU
address lines ADDR[15:13]. If these lines are selected as expansion address lines
in PGAR, but are not used in either window, the corresponding CPU address line
is output on the appropriate port G pin.
MXGS[2:1] — Memory Expansion Select for General-Purpose Chip Select 2 or 1
0 = General-purpose chip select 2 or 1 based on 64 Kbyte CPU address
1 = General-purpose chip select 2 or 1 based on expansion address
W2SZ[1:0] — Window 2 Size
These bits select the size of memory expansion window 2. Refer to the table following W1SZ[1:0].
Bits [3:2] — Not implemented
Always read zero
Table 5 CPU Address and Address Expansion Signals
Number of Banks
Window Size
8 Kbytes
16 Kbytes
32 Kbytes
32 Kbytes
(Window Based at
$4000)
ADDR[13:0]
XA[15:14]
ADDR[13:0]
XA[16:14]
ADDR[13:0]
XA[17:14]
ADDR[13:0]
XA[18:14]
—
—
—
—
2
ADDR[12:0]
XA13
ADDR[12:0]
XA[14:13]
ADDR[12:0]
XA[15:13]
ADDR[12:0]
XA[16:13]
ADDR[12:0]
XA[17:13]
ADDR[12:0]
XA[18:13]
ADDR[13:0]
XA14
ADDR[13:0]
XA[15:14]
ADDR[13:0]
XA[16:14]
ADDR[13:0]
XA[17:14]
ADDR[13:0]
XA[18:14]
—
—
ADDR[14:0]
XA15
ADDR[14:0]
XA[16:15]
ADDR[14:0]
XA[17:15]
ADDR[14:0]
XA[18:15]
—
—
—
—
4
8
16
32
64
PGAR
—
Port G Assignment
$002D
Bit 7
—
0
6
—
0
5
4
3
2
1
Bit 0
PGAR0
0
PGAR5
0
PGAR4
0
PGAR3
0
PGAR2
0
PGAR1
0
RESET:
MMSIZ
—
Memory Mapping Size
$0056
Bit 7
MXGS2
0
6
5
4
3
—
0
2
—
0
1
Bit 0
W1SZ0
0
MXGS1
0
W2SZ1
0
W2SZ0
0
W1SZ1
0
RESET:
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相关代理商/技术参数 |
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| M68HC11K2 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:CONFIG Register Programming for EEPROM-based M68HC11 Microcontrollers |
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