参数资料
型号: M68Z128N
厂商: 意法半导体
英文描述: 5V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable
中文描述: 5V的,1兆位的输出128KB的x8低功耗SRAM启用
文件页数: 4/12页
文件大小: 95K
代理商: M68Z128N
M68Z128
4/12
Figure 4. Block Diagram
AI00665
ROW
DECODER
A
A
(9)
CHIP ENABLE.
INPUT
DATA
CTRL
DQ
DQ
(8)
COLUMN
DECODER
I/O CIRCUITS
(8)
A
A
CHIP ENABLE.
E1
W
G
CHIP
ENABLE
MEMORY
ARRAY
VCC
VSS
E2
Table 6. DC Characteristics
(T
A
= 0 to 70°C; V
CC
= 5V ±10%)
Symbol
Note: 1. Average AC current, Outputs open, cycling at t
AVAV
minimum.
2. All other Inputs at V
IL
0.8V or V
IH
2.2V.
3. All other Inputs at V
IL
0.3V or V
IH
V
CC
–0.3V.
Parameter
Test Condition
Min
Typ
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
±1
μA
I
LO
Output Leakage Current
0V
V
OUT
V
CC
±1
μA
I
CC1 (1)
Supply Current
V
CC
= 5.5V, (-55)
30
70
mA
I
CC2 (2)
Supply Current (Standby) TTL
V
CC
= 5.5V, E1 = V
IH
or
E2 = V
IL
, f =0
0.1
2
mA
I
CC3 (3)
Supply Current (Standby) CMOS
V
CC
= 5.5V, E1
V
CC
– 0.3V
or E2
0.3V, f = 0
0.4
20
μA
V
IL
Input Low Voltage
–0.3
0.8
V
V
IH
Input High Voltage
2.2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage
I
OH
= –1mA
2.4
V
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