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参数资料
| 型号： | M6XXLFXI |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, QCC16 |
| 封装： | 3 X 3 MM, LEAD FREE, MO-220, QFN-24 |
| 文件页数： | 2/17页 |
| 文件大小： | 475K |
| 代理商： | M6XXLFXI |
MoBL Clock
M300/M600
Document Number: 001-12946 Rev. *C
Page 10 of 17
DC Electrical Specifications
The DC Electrical Spec. table for MoBL Clock M3xx/M6xx family (VDD_CLKX = 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V)
Parameter
Description
Conditions
Min
Typ
Max
Unit
VOL
Output Low Voltage, CLK pins
IOL = 2 mA, drive strength = [00]
–
0.4
V
IOL = 3 mA, drive strength = [01]
IOL = 7 mA, drive strength = [10]
IOL = 12 mA, drive strength = [11]
VOH
Output High Voltage, CLK pins
IOH = –2 mA, drive strength = [00]
VDD_CLKX –
0.4
––
V
IOH = –3 mA, drive strength = [01]
IOH = –7 mA, drive strength = [10]
IOH = –12 mA, drive strength = [11]
VOLSD
Output Low Voltage, SDA
IOL = 4 mA
–
0.4
V
VIL1
Input Low Voltage of PD#/OE,
SDA and SCL pins
–
0.2 × VDD
V
VIL2
Input Low Voltage of EXCLKIN
pin
–
0.1 × VDD
V
VIH1
Input High Voltage of PD#/OE,
SDA and SCL pins
0.8 × VDD
––
V
VIH2
Input High Voltage of EXCLKIN
for MoBL Clock M6xx
0.9 × VDD
––
V
VIH3
Input High Voltage of EXCLKIN
pin MoBL Clock M3xx
0.9 × VDD
–2.2
V
IIH
Input High Current, PD#/OE
VIH = VDD
–
10
A
IIL
Input Low Current, PD#/OE
VIL = 0V
–
10
A
RDN
Pull Down Resistor of clocks
(CLK1-CLK3) in off-state
Clock outputs in off-state by setting
PD# = Low
100
160
250
k
IDD[1,2]
Supply Current
All outputs running, CLOAD = 0
–
15
–
mA
IDDS[1]
Standby Current
PD# = Low, and
I2C circuit not in Keep
Alive Mode
–3
–
A
CIN[2]
Input Capacitance
SCL, SDA, and PD#/OE inputs
–
7
pF
Notes
1. This parameter is configuration dependent. The specified value is for the drive level setting of [1,1].
2. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs.
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