参数资料
型号: M7040N
厂商: 意法半导体
英文描述: 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE
中文描述: 64K的× 72位的网络数据包进入搜索引擎
文件页数: 4/159页
文件大小: 1088K
代理商: M7040N
M7040N
4/159
WRITE COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Single Location WRITE Cycle Timing (Figure 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Burst WRITE of the Data and Mask Arrays (BLEN = 4) (Figure 21.). . . . . . . . . . . . . . . . . . . . . . . . 37
(Single) WRITE Address Format for Data and Mask Arrays or SRAM (Table 23.) . . . . . . . . . . . . . 37
WRITE Address Format for Internal Registers (Table 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
WRITE Address Format for Data and Mask Array (Burst Write) (Table 25.). . . . . . . . . . . . . . . . . . 38
Parallel WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SEARCH COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
72-bit Configuration with Single Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Hardware Diagram for a Table with One Device (Figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
72-Bit Configuration SEARCH Timing Diagram for One Device (Figure 23.) . . . . . . . . . . . . . . . . . 40
x72 Table with One Device (Figure 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Latency of SEARCH from Instruction to SRAM Access Cycle, 72-bit (Table 26.). . . . . . . . . . . . . . 41
Shift of SSF and SSV from SADR (Table 27.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
72-bit SEARCH on Tables Configured as x72 Using up to Eight M7040N Devices. . . . . . . . . 42
Hit/Miss Assumption (Table 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Hardware Diagram for a Table with Eight Devices (Figure 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
x72 Table with Eight Devices (Figure 26.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Timing Diagrams for x72 Using up to Eight M7040N Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Latency of SEARCH from Instruction to SRAM Access Cycle (Table 29.) . . . . . . . . . . . . . . . . . . . 48
Shift of SSF and SSV from SADR (Table 30.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
72-bit Search on Tables Configured as x72 Using Up To 31 M7040N Devices . . . . . . . . . . . . 48
Hit/Miss Assumption (Table 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Hardware Diagram for a Table with 31 Devices (Figure 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Hardware Diagram for a Block of Up To Eight Devices (Figure 31.). . . . . . . . . . . . . . . . . . . . . . . . 51
x72 Table with 31 Devices (Figure 32.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Timing Diagrams for x72 Using Up To 31 M7040N Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Latency of SEARCH from Instruction to SRAM Access Cycle (Table 32.) . . . . . . . . . . . . . . . . . . . 64
Shift of SSF and SSV from SADR (Table 33.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
144-bit Configuration with Single Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Hardware Diagram for a Table with 1 Device (Figure 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Timing Diagram for a 144-bit SEARCH for 1 Device (Figure 45.) . . . . . . . . . . . . . . . . . . . . . . . . . . 66
x144 Table with One Device (Figure 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit (Table 34.). . . . . . . . . . . . . 67
Shift of SSF and SSV from SADR (Table 35.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
144-bit Search on Tables Configured as x144 Using Up to Eight M7040N Devices . . . . . . . . 68
Hit/Miss Assumption (Table 36.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Hardware Diagram for a Table with Eight Devices (Figure 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
x144 Table with Eight Devices (Figure 48.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Timing Diagrams for x144 Using Up to Eight M7040N Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit (Table 37.). . . . . . . . . . . . . 74
Shift of SSF and SSV from SADR (Table 38.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
相关PDF资料
PDF描述
M7040N-066ZA1T CAP 0.01PF 50V 10% X7R AXIAL BULK P-MIL-PRF-39014
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相关代理商/技术参数
参数描述
M7040N-066ZA1T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE
M7040N-083ZA1T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE
M7040N-100ZA1T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE
M7041 制造商:Tamura Corporation of America 功能描述:
M7045 制造商:Tamura Corporation of America 功能描述: