参数资料
型号: M74LCX16373DTR2G
厂商: ON Semiconductor
文件页数: 1/7页
文件大小: 0K
描述: IC LATCH TRANSP 16BIT 48TSSOP
标准包装: 1
系列: 74LCX
逻辑类型: D 型透明锁存器
电路: 8:8
输出类型: 三态
电源电压: 2 V ~ 3.6 V
独立电路: 2
延迟时间 - 传输: 1.5ns
输出电流高,低: 24mA,24mA
工作温度: -55°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 48-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 48-TSSOP
包装: 标准包装
其它名称: M74LCX16373DTR2GOSDKR
Semiconductor Components Industries, LLC, 2012
October, 2012 Rev. 11
1
Publication Order Number:
MC74LCX16373/D
MC74LCX16373
Low-Voltage CMOS 16-Bit
Transparent Latch
With 5 VTolerant Inputs and Outputs
(3State, NonInverting)
The MC74LCX16373 is a high performance, noninverting 16bit
transparent latch operating from a 2.3 V to 3.6 V supply. The device is
byte controlled. Each byte has separate Output Enable and Latch Enable
inputs. These control pins can be tied together for full 16bit operation.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
MC74LCX16373 inputs to be safely driven from 5.0 V devices.
The MC74LCX16373 contains 16 Dtype latches with 3state
5.0 Vtolerant outputs. When the Latch Enable (LEn) inputs are HIGH,
data on the Dn inputs enters the latches. In this condition, the latches are
transparent, i.e., a latch output will change state each time its D input
changes. When LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the HIGHtoLOW
transition of LE. The 3state outputs are controlled by the Output
Enable (OEn) inputs. When OE is LOW, the outputs are enabled. When
OE is HIGH, the standard outputs are in the high impedance state, but
this does not interfere with new data entering into the latches.
Features
Designed for 2.3 to 3.6 V VCC Operation
5.4 ns Maximum tpd
5.0 V Tolerant Interface Capability With 5.0 V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
LVTTL Compatible
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (20 mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 500 mA
ESD Performance:
Human Body Model >2000 V
Machine Model >200 V
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
MARKING DIAGRAM
TSSOP48
DT SUFFIX
CASE 1201
1
48
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
1
48
LCX16373G
AWLYYWW
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
相关PDF资料
PDF描述
1-796695-0 TERM BLOCK HEADER 10POS R/A .137
1-796694-0 TERM BLOCK HDR 10POS 3.5MM STR
284051-3 TERM BLOCK PLUG 3POS VERT .400
284045-3 TERM BLOCK PLUG 3POS VERT STACK
1-796698-1 TERM BLOCK HEADER 11POS R/A 5MM
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