参数资料
| 型号： | M74LCX16373DTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/7页 |
| 文件大小： | 0K |
| 描述： | IC LATCH TRANSP 16BIT 48TSSOP |
| 标准包装： | 1 |
| 系列： | 74LCX |
| 逻辑类型： | D 型透明锁存器 |
| 电路： | 8:8 |
| 输出类型： | 三态 |
| 电源电压： | 2 V ~ 3.6 V |
| 独立电路： | 2 |
| 延迟时间 - 传输： | 1.5ns |
| 输出电流高，低： | 24mA，24mA |
| 工作温度： | -55°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 48-TSSOP |
| 包装： | 标准包装 |
| 其它名称： | M74LCX16373DTR2GOSDKR |
MC74LCX16373
http://onsemi.com
4
DC ELECTRICAL CHARACTERISTICS
Symbol
Characteristic
Condition
TA = 55°C to +125°C
Units
Min
Max
VIH
HIGH Level Input Voltage (Note 2)
2.3 V ≤ VCC ≤ 2.7 V
1.7
V
2.7 V ≤ VCC ≤ 3.6 V
2.0
VIL
LOW Level Input Voltage (Note 2)
2.3 V ≤ VCC ≤ 2.7 V
0.7
V
2.7 V ≤ VCC ≤ 3.6 V
0.8
VOH
HIGH Level Output Voltage
2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA
VCC 0.2
V
VCC = 2.3 V; IOH = 8 mA
1.8
VCC = 2.7 V; IOH = 12 mA
2.2
VCC = 3.0 V; IOH = 18 mA
2.4
VCC = 3.0 V; IOH = 24 mA
2.2
VOL
LOW Level Output Voltage
2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA
0.2
V
VCC = 2.3 V; IOL = 8 mA
0.6
VCC = 2.7 V; IOL = 12 mA
0.4
VCC = 3.0 V; IOL = 16 mA
0.4
VCC = 3.0 V; IOL = 24 mA
0.55
IOZ
3State Output Current
VCC = 3.6 V, VIN = VIH or VIL,
VOUT = 0 to 5.5 V
±5
mA
IOFF
Power Off Leakage Current
VCC = 0, VIN = 5.5 V or VOUT = 5.5 V
10
mA
IIN
Input Leakage Current
VCC = 3.6 V, VIN = 5.5 V or GND
±5
mA
ICC
Quiescent Supply Current
VCC = 3.6 V, VIN = 5.5 V or GND
20
mA
DICC
Increase in ICC per Input
2.3 ≤ VCC ≤ 3.6 V; VIH = VCC 0.6 V
500
mA
2. These values of VI are used to test DC electrical characteristics only.
AC CHARACTERISTICS (tR = tF = 2.5 ns; CL = 50 pF; RL = 500 W)
Symbol
Parameter
Waveform
TA = 55°C to +125°C
Units
VCC = 3.3 V ± 0.3 V
CL = 50 pF
VCC = 2.7 V
CL = 50 pF
VCC = 2.5 V ± 0.2 V
CL = 30 pF
Min
Max
Min
Max
Min
Max
tPLH
tPHL
Propagation Delay
Dn to On
1
1.5
5.4
1.5
5.9
1.5
6.5
ns
tPLH
tPHL
Propagation Delay
LE to On
3
1.5
5.5
1.5
6.4
1.5
6.6
ns
tPZH
tPZL
Output Enable Time to
High and Low Level
2
1.5
6.1
1.5
6.5
1.5
7.9
ns
tPHZ
tPLZ
Output Disable Time From
High and Low Level
2
1.5
6.0
1.5
6.3
1.5
7.2
ns
ts
Setup Time, HIGH or LOW Dn to
LE
3
2.5
3.0
ns
th
Hold Time, HIGH or LOW Dn to LE
3
1.5
2.0
ns
tw
LE Pulse Width, HIGH
3
3.0
3.5
ns
tOSHL
tOSLH
OutputtoOutput Skew
(Note 3)
1.0
ns
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGHtoLOW (tOSHL) or LOWtoHIGH (tOSLH); parameter
guaranteed by design.
相关PDF资料 |
PDF描述 |
|---|---|
| 1-796695-0 | TERM BLOCK HEADER 10POS R/A .137 |
| 1-796694-0 | TERM BLOCK HDR 10POS 3.5MM STR |
| 284051-3 | TERM BLOCK PLUG 3POS VERT .400 |
| 284045-3 | TERM BLOCK PLUG 3POS VERT STACK |
| 1-796698-1 | TERM BLOCK HEADER 11POS R/A 5MM |
相关代理商/技术参数 |
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| M74LCX16373DTR2G-CUT TAPE | 制造商:ON 功能描述:MC74LCX16373 Series 2.3 to 3.6 V CMOS 16-Bit Transparent Latch - TSSOP-48 |
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