参数资料
型号: M902-01I156.2500LF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 156.25 MHz, OTHER CLOCK GENERATOR, CQCC36
封装: 9 X 9 MM, CERAMIC, LCC-36
文件页数: 3/8页
文件大小: 328K
代理商: M902-01I156.2500LF
M902-01 Datasheet Rev 2.1
3 of 8
Revised 24Jun2004
Integr ated Circuit Systems , Inc. Netw o r ki ng & C o mmun ica t io ns ww w. icst.com tel (5 08) 85 2-54 00
M902-01
VCSO BASED GBE CLOCK GENERATOR
Prod uct Data Sh eet
FUNCTIONAL DESCRIPTION
The M902-01 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks
synchronized to an input reference clock.
The M902-01 combines the flexibility of a VCSO
(Voltage Controlled SAW Oscillator) with the stability of
a crystal oscillator.
Input Reference
The input reference can either be an external, discrete
crystal or a stable external clock source such as a
packaged (temperature-compensated) crystal
oscillator.
If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal
should be a parallel-resonant, fundamental mode
crystal. Apply it to the XTAL_1 / REF_IN and XTAL_2 input
pins. External crystal load trim capacitors are also
If an external LVCMOS/LVTTL clock source is used,
apply it to the XTAL_1 / REF_IN input pin.
In either case, the reference clock is supplied to the
phase detector of the PLL. The M902-01 includes a
reference divider that divides the input reference
frequency by a fixed value “R” and provides the result to
the phase detector.
The EX_CLK pin is available for a clock feed-through
mode for testing. See “External Clock Feed-through”
The PLL
The PLL (Phase Locked Loop) includes the phase
detector, the VCSO, a feedback divider (labeled
“M Divider”), and a reference divider (“R Divider”).
The feedback divider divides the VCSO output
frequency by a fixed value “M” to match the reference
frequency provided to the phase detector by the
reference divider.
By controlling the frequency and phase of the VCSO,
the phase detector precisely locks the frequency and
phase of the feedback divider output to that of the
reference divider output.
The relationship between the VCSO output frequency,
the M Divider, the R Divider and the input reference
frequency is defined as follows:
For the M902-01-156.2500 (see “Ordering Information” on pg. 8):
VCSO output frequency = 156.25MHz
Input reference frequency = 25MHz
M=25
R= 4
Therefore, for the M902-01-156.2500:
25
156.25MHz = 25MHz
4
The product of the input crystal frequency and
falls within the lock range of the VCSO.
External Clock Feed-through
The EXT_CLK pin provides an input for an external
single-ended clock that directly drives the LVPECL
clock outputs. This pin is intended for system debugging
and performance evaluation..
STOP Clock
The STOP pin puts the output clock into a static condition.
EN_EXT_CLK
Logic 1 enables the EXT_CLK input.
Use Logic 0 for normal operation.
EXT_CLK
Apply an external LVCMOS/LVTTL clock source
for 0 to 200 MHz feed-through operation.
Leave inactive for normal operation.1
Note 1: In applications where EXT_CLK is active while the SAW PLL
signal path is enabled, it is necessary to gate the EXT_CLK to
minimize jitter in the LVPECL output pairs. See the PCB Design
Guidelines for ICS SAW PLLs application note at
Logic 1 Output clocks are static
Logic 0 Output clocks enabled for normal operation
Fvcso
Fxtal
M
R
-----
×
=
----------
×
M
R
-----
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