参数资料
型号: M93S56-WDW6TG
厂商: 意法半导体
英文描述: Triple 3-Input Positive-AND Gates 14-TSSOP -40 to 85
中文描述: 4Kbit,2Kbit和1Kbit 16位宽MICROWIRE串行EEPROM的访问与街区保护
文件页数: 24/34页
文件大小: 525K
代理商: M93S56-WDW6TG
M93S66, M93S56, M93S46
24/34
Table 18. AC Characteristics (M93Sx6-W, Device Grade 3)
Note: 1. t
CHCL
+ t
CLCH
1 / f
C
.
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. New product: identified by Process Identification letter W or G.
Test conditions specified in
Table 9.
and
Table 6.
Symbol
Alt.
Parameter
Min.
3
Max.
3
Unit
f
C
f
SK
Clock Frequency
D.C.
2
MHz
t
PRVCH
t
PRES
Protect Enable Valid to Clock High
50
ns
t
WVCH
t
PES
Write Enable Valid to Clock High
50
ns
t
CLPRX
t
PREH
Clock Low to Protect Enable Transition
0
ns
t
SLWX
t
PEH
Chip Select Low to Write Enable Transition
250
ns
t
SLCH
Chip Select Low to Clock High
50
ns
t
SHCH
t
CSS
Chip Select Set-up Time
50
ns
t
SLSH2
t
CS
Chip Select Low to Chip Select High
200
ns
t
CHCL1
t
SKH
Clock High Time
200
ns
t
CLCH1
t
SKL
Clock Low Time
200
ns
t
DVCH
t
DIS
Data In Set-up Time
50
ns
t
CHDX
t
DIH
Data In Hold Time
50
ns
t
CLSH
t
SKS
Clock Set-up Time (relative to S)
50
ns
t
CLSL
t
CSH
Chip Select Hold Time
0
ns
t
SHQV
t
SV
Chip Select to Ready/Busy Status
200
ns
t
SLQZ
t
DF
Chip Select Low to Output Hi-Z
100
ns
t
CHQL
t
PD0
Delay to Output Low
200
ns
t
CHQV
t
PD1
Delay to Output Valid
200
ns
t
W
t
WP
Erase/Write Cycle time
5
ms
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