参数资料
型号: M93S56-WDW6TG
厂商: 意法半导体
英文描述: Triple 3-Input Positive-AND Gates 14-TSSOP -40 to 85
中文描述: 4Kbit,2Kbit和1Kbit 16位宽MICROWIRE串行EEPROM的访问与街区保护
文件页数: 5/34页
文件大小: 525K
代理商: M93S56-WDW6TG
5/34
M93S66, M93S56, M93S46
An internal Power-on Data Protection mechanism
in the M93Sx6 inhibits the device when the supply
is too low.
POWER-ON DATA PROTECTION
To prevent data corruption and inadvertent write
operations during power-up, a Power-On Reset
(POR) circuit resets all internal programming cir-
cuitry, and sets the device in the Write Disable
mode.
At Power-up and Power-down, the device
must
not
be selected (that is, Chip Select Input
(S) must be driven Low) until the supply
voltage reaches the operating value V
CC
specified in
Table 5.
to
Table 6.
.
When V
CC
reaches its valid level, the device is
properly reset (in the Write Disable mode) and
is ready to decode and execute incoming
instructions.
For the M93Sx6 devices (5V range) the POR
threshold voltage is around 3V. For the M93Sx6-
W (3V range) and M93Sx6-R (2V range) the POR
threshold voltage is around 1.5V.
INSTRUCTIONS
The instruction set of the M93Sx6 devices con-
tains seven instructions, as summarized in
Table
2.
to
Table 3.
. Each instruction consists of the fol-
lowing parts, as shown in
Figure 4.
:
Each instruction is preceded by a rising edge
on Chip Select Input (S) with Serial Clock (C)
being held Low.
A start bit, which is the first ‘1’ read on Serial
Data Input (D) during the rising edge of Serial
Clock (C).
Two op-code bits, read on Serial Data Input
(D) during the rising edge of Serial Clock (C).
(Some instructions also use the first two bits of
the address to define the op-code).
The address bits of the byte or word that is to
be accessed. For the M93S46, the address is
made up of 6 bits (see
Table 2.
). For the
M93S56 and M93S66, the address is made up
of 8 bits (see
Table 3.
).
The M93Sx6 devices are fabricated in CMOS
technology and are therefore able to run as slow
as 0 Hz (static input signals) or as fast as the max-
imum ratings specified in
Table 16.
to
Table 19.
.
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