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参数资料
| 型号： | M93S66-DW1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 256 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
| 封装： | 0.169 INCH, PLASTIC, TSSOP-8 |
| 文件页数： | 4/23页 |
| 文件大小： | 163K |
| 代理商： | M93S66-DW1 |
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). When a READ instruction
is received, the instruction and address are de-
coded and the data from the memory is transferred
into an output shift register. A dummy ’0’ bit is output
first followed by the 16 bit word with the MSB first.
Output data changes are triggered by the Low to
High transition of the Clock (C). The M93Sx6 will
automatically increment the address and will clock
out the next word as long as the Chip Select input
(S) is held High. In this case the dummy ’0’ bit is
NOT output between words and a continuous
stream of data can be read.
Write Enable and Write Disable
The Write Enable instruction (WEN) authorizes the
following Write instructions to be executed. The
Write Disable instruction (WDS) disables the exe-
cution of the following Write instructions and the
internal programming cycle cannot run.
When power is first applied, the M93Sx6 is in Write
Disable mode and all Write instructions are inhib-
ited. When the WEN instruction is executed, Write
instructions remain enabled until a Write Disable
instruction (WDS) is executed or VCC falls below
the Power-On Reset threshold Voltage.
To protect the memory contents from accidental
corruption, it is advisable to issue the WDS instruc-
tion after every write cycle. The READ instruction
is not affected by the WEN or WDS instructions.
Write
The Write instruction (WRITE) is composed of the
Start bit plus the Op-Code followed by the address
and the 16 data bits to be written. The Write Enable
signal (W) must be held high during the Write
instruction. Data input (D) is sampled on the Low
to High transition of the clock. After the last data bit
has been sampled, Chip Select (S) must be
brought Low before the next rising edge of the clock
(C) in order to start the self-timed programming
cycle. This is really important as, if S is brought low
before or after this specific frame window, the
addressed location will not be programmed, provid-
ing that the address in NOT in the protected area.
If the M93Sx6 is still performing the write cycle, the
Busy signal (Q = 0) will be returned if the Chip
Select input (S) is driven high after the tSLSH delay,
and the M93Sx6 will ignore any data on the bus.
When the write cycle is completed, the Ready
signal (Q = 1) will indicate (if S is driven high) that
the M93Sx6 is ready to receive a new instruction.
Programming is internally self-timed (the external
clock signal on C input may be disconnected or left
running after the start of a Write cycle).
Page Write
A Page Write instruction (PAWRITE) contains the
first address to be written followed by up to 4 data
words. The Write Enable signal (W) must be held
High during the PAWRITE instruction. Input ad-
dress and data are sampled on the Low to High
transition of the clock. After the receipt of each data
word, bits A1-A0 of the internal address register are
incremented, the high order bits (Ax-A2) remaining
unchanged. Users must take care by software to
ensure that the last word address has the same
upper order address bits as the initial address
transmitted to avoid address roll-over. After the LSB
of the last data word, Chip Select (S) must be
brought Low before the next rising edge of the
Clock (C) in order to start the self-timed program-
ming cycle. This is really important as, if S is
brought low before or after this specific frame win-
dow, the addressed locations will not be pro-
grammed. The Page Write operation will not be
performed if any of the 4 words is addressing the
protected area. If the M93Sx6 is still performing the
programming cycle, the Busy signal (Q = 0) will be
returned if the Chip Select input (S) is driven high,
and the M93Sx6 will ignore any data on the bus.
When the write cycle is completed, the Ready
signal (Q = 1) will indicate (if S is driven high) that
the M93Sx6 is ready to receive a new instruction.
Write All
The Write All instruction (WRALL) is valid only after
the Protect Register has been cleared by executing
a PRCLEAR (Protect Register Clear) instruction.
The Write All instruction simultaneously writes the
whole memory with the same data word included
in the instruction. The Write Enable signal (W) must
be held High before and during the Write All instruc-
tion. Input address and data are sampled on the
Low to High transition of the clock. If the M93Sx6
is still performing the write cycle, the Busy signal
(Q = 0) will be returned if the Chip Select input (S)
is driven high after the tSLSH delay, and the M93Sx6
will ignore any data on the bus. When the write
cycle is completed, the Ready signal (Q = 1) will
indicate (if S is driven high) that the M93Sx6 is
ready to receive a new instruction.
READY/BUSY Status
During every programming cycle (after a WRITE,
WRALL or PAWRITE instruction) the Data Output
(Q) indicates the Ready/Busy status of the memory
when the Chip Select is driven High. Once the
M93Sx6 is Ready, the Data Output is set to ’1’ until
a new start bit is decoded or the Chip Select is
brought Low.
12/23
M93S66, M93S56, M93S46
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M93S66-DW3 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
| M93S66-DW3G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
| M93S66-DW3P | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
| M93S66-DW3T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
| M93S66-DW3TG | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
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