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参数资料
| 型号： | M95080BN |
| 厂商： | 意法半导体 |
| 英文描述： | Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs 20-TSSOP -40 to 85 |
| 中文描述： | 64/32/16/8千位串行SPI总线的EEPROM高速时钟 |
| 文件页数： | 15/39页 |
| 文件大小： | 590K |
| 代理商： | M95080BN |
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15/39
M95640, M95320
Figure 12. Write Status Register (WRSR) Sequence
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction al-
lows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in Figure 12.
The Write Status Register (WRSR) instruction has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) that latches in the eighth
bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status
Register (WRSR) instruction is not executed. As
soon as Chip Select (S) is driven High, the self-
timed Write Status Register cycle (whose duration
is t
W
) is initiated. While the Write Status Register
cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 dur-
ing the self-timed Write Status Register cycle, and
is 0 when it is completed. When the cycle is com-
pleted, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that is to be treated as read-only, as defined
in Table 2.
The Write Status Register (WRSR) instruction also
allows the user to set or reset the Status Register
Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected Mode (HPM). The Write Status Register
(WRSR) instruction is not executed once the Hard-
ware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable
(SRWD) and Block Protect (BP1, BP0) bits are fro-
zen at their current values from just before the
start of the execution of Write Status Register
(WRSR) instruction. The new, updated, values
take effect at the moment of completion of the ex-
ecution of Write Status Register (WRSR) instruc-
tion.
C
D
AI02282D
S
Q
2
1
3
4
5
6
7
8
9 10 11 12 13 14 15
High Impedance
Instruction
Status
Register In
0
7
6
5
4
3
2
0
1
MSB
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| M95080-BN3 | 功能描述:电可擦除可编程只读存储器 5.5V 8K (1Kx8) RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| M95080-BN6 | 功能描述:电可擦除可编程只读存储器 5.5V 8K (1Kx8) RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| M95080-BPMN6 | 功能描述:电可擦除可编程只读存储器 5.5V 8K (1Kx8) RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| M95080-DFDW6TP | 功能描述:IC EEPROM 8KBIT 10MHZ 8TSSOP 制造商:stmicroelectronics 系列:- 包装:剪切带（CT） 零件状态:有效 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K（1K x 8） 速度:5MHz 接口:SPI 串行 电压 - 电源:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C（TA） 封装/外壳:8-TSSOP（0.173"，4.40mm 宽） 供应商器件封装:8-TSSOP 标准包装:1 |
| M95080-DFMC6TG | 功能描述:IC EEPROM 8KB I2C SPI 8UFDFPN 制造商:stmicroelectronics 系列:- 包装:剪切带（CT） 零件状态:有效 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K（1K x 8） 速度:5MHz 接口:SPI 串行 电压 - 电源:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C（TA） 封装/外壳:8-UFDFN 裸露焊盘 供应商器件封装:8-UFDFPN（2x3） 标准包装:1 |
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