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参数资料
| 型号： | MA300014 |
| 厂商： | Microchip Technology |
| 文件页数： | 11/92页 |
| 文件大小： | 0K |
| 描述： | MODULE DSPIC30F SAMPLE 80QFP |
| 标准包装： | 1 |
| 附件类型： | 插拔式模块（PIM）- dsPIC30F6014A |
| 适用于相关产品： | dsPICDEM 板（DM300014 或 DM300019） |
| 产品目录页面： | 658 (CN2011-ZH PDF) |
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dsPIC30F
5.1.2
ADDRESSING MODES OVERVIEW
The dsPIC30F supports 16/16 and 32/16 divide
Overhead free circular buffers (modulo addressing) are
supported in both X and Y address spaces. The
modulo addressing removes the software boundary
checking overhead for DSP algorithms. Furthermore,
the X AGU circular addressing can be used with any of
the MCU class of instructions. The X AGU also
supports bit-reversed addressing to greatly simplify
input or output data reordering for radix-2 FFT
algorithms.
operations, both fractional and integer. All divide
instructions are iterative operations. They must be
executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those 19
cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift, in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
The CPU supports Inherent (no operand), Relative,
Literal, Memory Direct, Register Direct and Register
5.1.5
INTERRUPT OVERVIEW
Indirect Addressing modes. Each instruction is
associated with a predefined addressing mode group
depending upon its functional requirements. As many
as 6 addressing modes are supported for each
The dsPIC30F has a vectored exception scheme with
up to 8 sources of non-maskable traps and 54 interrupt
sources. Each interrupt source can be assigned to one
of seven priority levels.
instruction.
For most instructions, the dsPIC30F is capable of
executing a data (or program data) memory read, a
5.1.6
FEATURES TO ENHANCE
COMPILER EFFICIENCY
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
In addition to extensive DSP capability, the CPU
architecture possesses several features that lead to a
more efficient (code size and speed) C compiler.
supported, allowing A + B = C operations to be
executed in a single cycle.
1.
For most instructions, three-parameter instruc-
tions can be supported, allowing A + B = C
5.1.3
DSP ENGINE OVERVIEW
2.
operations to be executed in a single cycle.
Instruction addressing modes are extremely
The DSP engine features a high speed, 17-bit by 17-bit
flexible to meet compiler needs.
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits right or left, in a single cycle. The DSP
instructions operate seamlessly with all other
instructions and have been designed for optimal real-
time performance. The MAC instruction and other
associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM memory data space
be split for these instructions and linear for all others.
Data space partitioning is achieved in a transparent
and flexible manner through dedicating certain working
registers to each address space.
3.
4.
5.
6.
The working register array consists of 16 x 16-bit
registers, each of which can act as data,
address or offset registers. One working register
(W15) operates as the software Stack Pointer
for interrupts and calls.
Linear indirect access of all data space is
possible, plus the memory direct address range
is up to 8 Kbytes. This capability, together with
the addition of 16-bit direct address MOV based
instructions, has provided a contiguous linear
addressing space.
Linear indirect access of 32 Kword (64 Kbyte)
pages within program space is possible, using
any working register via new table read and
write instructions.
Part of data space can be mapped into program
5.1.4
SPECIAL MCU FEATURES
space, allowing constant data to be accessed as
The dsPIC30F features a 17-bit by 17-bit single-cycle
multiplier that is shared by both the MCU ALU and DSP
engine. The multiplier can perform signed, unsigned
and mixed-sign multiplication. Using a 17-bit by 17-bit
multiplier for 16-bit by 16-bit multiplication not only
allows you to perform mixed-sign multiplication, it also
achieves accurate results for special operations such
as (-1.0) x (-1.0).
? 2005 Microchip Technology Inc.
if it were in data space.
DS70043F-page 9
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| MA300015 | 功能描述:子卡和OEM板 dsPIC30F 80L Plug In Sample (6010A). RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
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| MA300128 | 功能描述:子卡和OEM板 _ RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
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