- 您现在的位置：买卖IC网 > PDF目录17016 > MA330011 (Microchip Technology)MODULE DSPIC33 100P TO 100QFP PDF资料下载
参数资料
| 型号： | MA330011 |
| 厂商： | Microchip Technology |
| 文件页数： | 83/199页 |
| 文件大小： | 0K |
| 描述： | MODULE DSPIC33 100P TO 100QFP |
| 标准包装： | 1 |
| 附件类型： | 插拔式模块（PIM）- dsPIC33FJ256GP710 |
| 适用于相关产品： | Explorer 16（DM240001 或 DM240002） |
| 产品目录页面： | 658 (CN2011-ZH PDF) |
| 相关产品： | DSPIC33FJ64GP710T-I/PT-ND - IC DSPIC MCU/DSP 64K 100TQFP DSPIC33FJ64GP710T-I/PF-ND - IC DSPIC MCU/DSP 64K 100TQFP DSPIC33FJ64GP310T-I/PT-ND - IC DSPIC MCU/DSP 64K 100TQFP DSPIC33FJ64GP310T-I/PF-ND - IC DSPIC MCU/DSP 64K 100TQFP DSPIC33FJ256GP510T-I/PT-ND - IC DSPIC MCU/DSP 256K 100TQFP DSPIC33FJ256GP510T-I/PF-ND - IC DSPIC MCU/DSP 256K 100TQFP DSPIC33FJ128GP310T-I/PT-ND - IC DSPIC MCU/DSP 128K 100TQFP DSPIC33FJ128GP310T-I/PF-ND - IC DSPIC MCU/DSP 128K 100TQFP DSPIC33FJ256GP710T-I/PT-ND - IC DSPIC MCU/DSP 256K 100TQFP DSPIC33FJ256GP710T-I/PF-ND - IC DSPIC MCU/DSP 128K 100TQFP 更多... |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页当前第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页第196页第197页第198页第199页
2007 Microchip Technology Inc.
Preliminary
DS70165E-page 171
dsPIC33F
14.0
OUTPUT COMPARE
14.1
Setup for Single Output Pulse
Generation
When the OCM control bits (OCxCON<2:0>) are set to
‘100’, the selected output compare channel initializes
the OCx pin to the low state and generates a single
output pulse.
To generate a single output pulse, the following steps
are required (these steps assume timer source is
initially turned off but this is not a requirement for the
module operation):
1.
Determine the instruction clock cycle time. Take
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
2.
Calculate time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
3.
Calculate the time to the falling edge of the pulse
based on the desired pulse width and the time to
the rising edge of the pulse.
4.
Write the values computed in steps 2 and 3 above
into the Output Compare register, OCxR, and the
Output Compare Secondary register, OCxRS,
respectively.
5.
Set Timer Period register, PRy, to value equal to
or greater than value in OCxRS, the Output
Compare Secondary register.
6.
Set the OCM bits to ‘100’ and the OCTSEL
(OCxCON<3>) bit to the desired timer source.
The OCx pin state will now be driven low.
7.
Set the TON (TyCON<15>) bit to ‘1’, which
enables the compare time base to count.
8.
Upon the first match between TMRy and OCxR,
the OCx pin will be driven high.
9.
When the incrementing timer, TMRy, matches
the
Output
Compare
Secondary
register,
OCxRS, the second and trailing edge (high-to-
low) of the pulse is driven onto the OCx pin. No
additional pulses are driven onto the OCx pin
and it remains at low. As a result of the second
compare match event, the OCxIF interrupt flag
bit is set, which will result in an interrupt if it is
enabled, by setting the OCxIE bit. For further
information on peripheral interrupts, refer to
10. To initiate another single pulse output, change the
Timer and Compare register settings, if needed,
and then issue a write to set the OCM bits to ‘100’.
Disabling and re-enabling of the timer, and clear-
ing the TMRy register, are not required but may
be advantageous for defining a pulse from a
known event time boundary.
The output compare module does not have to be dis-
abled after the falling edge of the output pulse. Another
pulse can be initiated by rewriting the value of the
OCxCON register.
14.2
Setup for Continuous Output
Pulse Generation
When the OCM control bits (OCxCON<2:0>) are set to
‘101’, the selected output compare channel initializes
the OCx pin to the low state and generates output
pulses on each and every compare match event.
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required (these steps assume timer source is
initially turned off but this is not a requirement for the
module operation):
1.
Determine the instruction clock cycle time. Take
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
2.
Calculate time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
3.
Calculate the time to the falling edge of the pulse,
based on the desired pulse width and the time to
the rising edge of the pulse.
4.
Write the values computed in step 2 and 3 above
into the Output Compare register, OCxR, and the
Output Compare Secondary register, OCxRS,
respectively.
5.
Set Timer Period register, PRy, to a value equal to
or greater than value in OCxRS, the Output
Compare Secondary register.
6.
Set the OCM bits to ‘101’ and the OCTSEL bit to
the desired timer source. The OCx pin state will
now be driven low.
7.
Enable the compare time base by setting the TON
(TyCON<15>) bit to ‘1’.
8.
Upon the first match between TMRy and OCxR,
the OCx pin will be driven high.
9.
When the compare time base, TMRy, matches
the Output Compare Secondary register, OCxRS,
the second and trailing edge (high-to-low) of the
pulse is driven onto the OCx pin.
10. As a result of the second compare match event,
the OCxIF interrupt flag bit is set.
11. When the compare time base and the value in its
respective Timer Period register match, the TMRy
register resets to 0x0000 and resumes counting.
12. Steps 8 through 11 are repeated and a continu-
ous stream of pulses is generated, indefinitely.
The OCxIF flag is set on each OCxRS-TMRy
compare match event.
Note:
This data sheet summarizes the features
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
相关PDF资料 |
PDF描述 |
|---|---|
| MA320001 | MODULE PLUG-IN PIC32 100QFP |
| RBM08DRMT-S288 | CONN EDGECARD 16POS .156 EXTEND |
| GSM12DTKN-S288 | CONN EDGECARD 24POS .156 EXTEND |
| AC002021 | CABLE MPLAB PM3 ICSP |
| GSM12DTKH-S288 | CONN EDGECARD 24POS .156 EXTEND |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MA330011 | 制造商:Microchip Technology Inc 功能描述:dsPIC33 GP 100P to 100P TQFP Plug-In Mod |
| MA330012 | 功能描述:子卡和OEM板 dsPIC33F GP 100P to 84P Plug In Module RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| MA330013 | 功能描述:子卡和OEM板 dsPIC33F Plug In Module RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| MA330014 | 功能描述:子卡和OEM板 dsPIC33 MC RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| MA330015 | 功能描述:子卡和OEM板 dsPIC33 GP RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
发布紧急采购，3分钟左右您将得到回复。