参数资料
型号: MAC7111MAG40
厂商: Freescale Semiconductor
文件页数: 21/56页
文件大小: 0K
描述: IC MCU 32BIT FLASH 144-LQFP
标准包装: 60
系列: MAC7xxx
核心处理器: ARM7
芯体尺寸: 32-位
速度: 40MHz
连通性: CAN,EBI/EMI,I²C,SCI,SPI
外围设备: DMA,POR
输入/输出数: 112
程序存储器容量: 544KB(544K x 8)
程序存储器类型: 闪存
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 2.35 V ~ 5.5 V
数据转换器: A/D 16x8/10b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 144-LQFP
包装: 托盘
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Electrical Characteristics
Freescale Semiconductor
28
3.10.3 ATD Timing Specifications
Figure 10. ATD External Trigger Timing Diagram
Table 31. ATD External Trigger Timing Specifications
Num C
Parameter
Symbol
Min
Max
Unit
T1
D ETRIG Period (Level-Sensitive Trigger Mode)
TPERIOD 1 + NCONVn
1
NOTES:
1. NCONVn denotes 8- or 10-bit conversion time (refer to specifications N4, N5, P4 and P5). In order to achieve the
minimum period between conversions when using level-sensitive triggering, ETRIG must remain asserted this long.
fATDCLK Cycles
T2
D ETRIG Minimum Pulse Width
Edge-Sensitive Trigger Mode
Level-Sensitive Trigger Mode
tPW
1
2
fATDCLK Cycles
T3
D ETRIG Level Recovery 2
2. Time prior to the end of a conversion that ETRIG must be negated in order to prevent the start of another conversion.
tLR
1—
fATDCLK Cycles
T4
D Conversion Start Delay
tDLY
—2
fATDCLK Cycles
Level Sensitive
Low Active
Sequence
Conversion Activity
Complete Flag
Low Active
Sequence
Complete Flag
Conversion Activity
Level Sensitive
Falling Edge Active
Conversion Activity
Edge Sensitive
ETRIG
ANn_x
ETRIG
ASCIF
ANn_x
ETRIG
ASCIF
ANn_x
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