参数资料
型号: MAC7111MAG40
厂商: Freescale Semiconductor
文件页数: 22/56页
文件大小: 0K
描述: IC MCU 32BIT FLASH 144-LQFP
标准包装: 60
系列: MAC7xxx
核心处理器: ARM7
芯体尺寸: 32-位
速度: 40MHz
连通性: CAN,EBI/EMI,I²C,SCI,SPI
外围设备: DMA,POR
输入/输出数: 112
程序存储器容量: 544KB(544K x 8)
程序存储器类型: 闪存
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 2.35 V ~ 5.5 V
数据转换器: A/D 16x8/10b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 144-LQFP
包装: 托盘
ElectricalCharacteristics
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
29
3.11 Serial Peripheral Interface
3.11.1 Master Mode
Master mode timing values are shown in Table 32 and illustrated in Figure 11 and Figure 12.
3.11.2 Slave Mode
Slave mode timing values are shown in Table 33 and illustrated in Figure 13 and Figure 14.
Table 32. SPI Master Mode Timing Characteristics
Conditions are shown in Table 7 unless otherwise noted, CLOAD = 200 pF on all outputs
Num C
Rating
Symbol
Min
Typ
Max
Unit
U1a
P Operating Frequency (baud rate)
fOP
1
NOTES:
1. Refer to MAC7100 Microcontroller Family Reference Manual (MAC7100RM) Chapter 22 for all available baud rates.
2
2. On mask set L49P and L47W devices, U1a maximum = and U1b minimum = 4.
fIPS
U1b
P SCK Period (tSCK = 1 ÷ fOP, tIPS = 1 ÷ fIPS)tSCK
2 2
—7
× 32,768
tIPS
U2
D Enable Lead Time
tlead
tSCK
U3
D Enable Lag Time
tlag
tSCK
U4
D Clock (SCK) High or Low Time
twsck
tIPS 30
1024 tIPS
ns
U5
D Data Setup Time (Inputs)
tsu
25
ns
U6
D Data Hold Time (Inputs)
thi
0—
ns
U9
D Data Valid (after Enable Edge)
tv
——
25
ns
U10
D Data Hold Time (Outputs)
tho
0—
ns
U11
D Rise Time Inputs and Outputs
tr
——
25
ns
U12
D Fall Time Inputs and Outputs
tf
——
25
ns
Table 33. SPI Slave Mode Timing Characteristics
Conditions are shown in Table 7 unless otherwise noted, CLOAD = 200 pF on all outputs
Num C
Rating
Symbol
Min
Typ
Max
Unit
V1a
P Operating Frequency
fOP
1
NOTES:
1. On mask set L49P and L47W devices, V1a maximum = and V1b minimum = 4.
fIPS
V1b
P SCK Period (tSCK = 1 ÷ fOP, tIPS = 1 ÷ fIPS)tSCK
2 1
—7
× 32,768
tIPS
V2
D Enable Lead Time
tlead
1—
tIPS
V3
D Enable Lag Time
tlag
1—
tIPS
V4
D Clock (SCK) High or Low Time
twsck
tIPS 30
ns
V5
D Data Setup Time (Inputs)
tsu
25
ns
V6
D Data Hold Time (Inputs)
thi
25
ns
V7
D Slave Access Time
ta
——
1
tIPS
V8
D Slave SIN Disable Time
tdis
——
1
tIPS
V9
D Data Valid (after SCK Edge)
tv
——
25
ns
V10
D Data Hold Time (Outputs)
tho
0—
ns
V11
D Rise Time Inputs and Outputs
tr
——
25
ns
V12
D Fall Time Inputs and Outputs
tf
——
25
ns
1
732 678
,
×
-----------------------------
1
732 678
,
×
-----------------------------
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