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参数资料
| 型号： | MACH445-12 |
| 厂商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Density EE CMOS Programmable Logic |
| 中文描述： | 高密度电子工程CMOS可编程逻辑 |
| 文件页数： | 1/28页 |
| 文件大小： | 214K |
| 代理商： | MACH445-12 |
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Publication#
17468
Issue Date:
May 1995
Rev.
E
Amendment
/0
FINAL
MACH445-12/15/20
High-Density EE CMOS Programmable Logic
COM’L: -12/15/20
DISTINCTIVE CHARACTERISTICS
I
100-pin version of the MACH435 in PQFP
I
5 V, in-circuit programmable
I
JTAG, IEEE 1149.1 JTAG testing capability
I
128 macrocells
I
12 ns t
PD
I
83 MHz f
CNT
I
70 inputs with pull-up resistors
I
64 outputs
I
192 flip-flops
— 128 macrocell flip-flops
— 64 input flip-flops
I
Up to 20 product terms per function, with XOR
I
Flexible clocking
— Four global clock pins with selectable edges
— Asynchronous mode available for each
macrocell
I
8 “PAL33V16” blocks
I
Input and output switch matrices for high
routability
I
Fixed, predictable, deterministic delays
I
JEDEC-file compatible with MACH435
I
Zero-hold-time input register option
GENERAL DESCRIPTION
The MACH445 is a member of the high-performance
EE CMOS MACH 4 family. This device has approxi-
mately twelve times the macrocell capability of the
popular PAL22V10, with significant density and func-
tional features that the PAL22V10 does not provide. It is
architecturally identical to the MACH435, with the
addition of JTAG and 5-V programming features.
The MACH445 consists of eight PAL blocks intercon-
nected by a programmable central switch matrix. The
central switch matrix connects the PAL blocks to each
other and to all input pins, providing a high degree of
connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
Routability is further enhanced by an input switch matrix
and an output switch matrix. The input switch matrix
provides input signals with alternative paths into the
central switch matrix; the output switch matrix provides
flexibility in assigning macrocells to I/O pins.
The MACH445 has macrocells that can be configured
as synchronous or asynchronous. This allows
designers to implement both synchronous and
asynchronous logic together on the same device. The
two types of design can be mixed in any proportion,
since the selection on each macrocell affects only that
macrocell.
Up to 20 product terms per function can be assigned. It
is possible to allocate some product terms away from a
macrocell without losing the use of that macrocell for
logic generation.
The MACH445 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type, T-type, J-K, or S-R to help reduce
the number of product terms used. The flip-flop can also
be configured as a latch. The register type decision can
be made by the designer or by the software.
All macrocells can be connected to an I/O cell through
the output switch matrix. The output switch matrix
makes it possible to make significant design changes
while minimizing the risk of pinout changes.
Lattice Semiconductor
相关PDF资料 |
PDF描述 |
|---|---|
| MACH445-12YC | High-Density EE CMOS Programmable Logic |
| MACH445-15YC | High-Density EE CMOS Programmable Logic |
| MACH445-20YC | High-Density EE CMOS Programmable Logic |
| MACH5 | Fifth Generation MACH Architecture |
| MACHLV210-12 | High Density EE CMOS Programmable Logic |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MACH44512YC | 制造商:LATTICE 功能描述:_ |
| MACH445-12YC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACH445-15YC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
| MACH445-20YC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
| MACH465-12YC | 制造商:Advanced Micro Devices 功能描述: |
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