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参数资料
| 型号： | MACH445-12YC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | High-Density EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 12 ns, PQFP100 |
| 封装： | PLASTIC, QFP-100 |
| 文件页数： | 24/28页 |
| 文件大小： | 214K |
| 代理商： | MACH445-12YC |
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24
MACH445-12/15/20
f
MAX
PARAMETERS
The parameter f
MAX
is the maximum clock rate at which
the device is guaranteed to operate. Because the flexi-
bility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, f
MAX
is specified for
three types of synchronous designs.
The first type of design is a state machine with feedback
signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the in-
put setup time for the external signals (t
S
+ t
CO
). The re-
ciprocal, f
MAX
, is the maximum frequency with external
feedback or in conjunction with an equivalent speed de-
vice. This f
MAX
is designated “f
MAX
external.”
The second type of design is a single-chip state ma-
chine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop out-
puts. Under these conditions, the period is limited by the
internal delay from the flip-flop outputs through the inter-
nal feedback and logic to the flip-flop inputs. This f
MAX
is
designated “f
MAX
internal”. A simple internal counter is a
good example of this type of design; therefore, this pa-
rameter is sometimes called “f
CNT.
”
The third type of design is a simple data path applica-
tion. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (t
S
+ t
H
). However,
a lower limit for the period of each f
MAX
type is the mini-
mum clock period (t
WH
+ t
WL
). Usually, this minimum
clock period determines the period for the third f
MAX
, des-
ignated “f
MAX
no feedback.”
For devices with input registers, one additional f
MAX
pa-
rameter is specified: f
MAXIR
. Because this involves no
feedback, it is calculated the same way as f
MAX
no feed-
back. The minimum period will be limited either by the
sum of the setup and hold times (t
SIR
+ t
HIR
) or the sum of
the clock widths (t
WICL
+ t
WICH
). The clock widths are nor-
mally the limiting parameters, so that f
MAXIR
is specified
as 1/(t
WICL
+ t
WICH
). Note that if both input and output reg-
isters are use in the same path, the overall frequency will
be limited by t
ICS
.
All frequencies except f
MAX
internal are calculated from
other measured AC parameters. f
MAX
internal is meas-
ured directly.
t
HIR
t
SIR
LOGIC
REGISTER
t
t
CLK
(SECOND
CHIP)
S
CO
t
S
f
MAX
External; 1/(t
S
+ t
CO
)
LOGIC
REGISTER
CLK
f
MAX
Internal (f
CNT
)
LOGIC
REGISTER
t
CLK
S
f
MAX
No Feedback; 1/(t
S
+ t
H
) or 1/(t
WH
+ t
WL
)
17468E-23
LOGIC
REGISTER
CLK
f
MAXIR
; 1/(t
SIR
+ t
HIR
) or 1/(t
WICL
+ t
WICH
)
相关PDF资料 |
PDF描述 |
|---|---|
| MACH445-15YC | High-Density EE CMOS Programmable Logic |
| MACH445-20YC | High-Density EE CMOS Programmable Logic |
| MACH5 | Fifth Generation MACH Architecture |
| MACHLV210-12 | High Density EE CMOS Programmable Logic |
| MACHLV210-12JC | High Density EE CMOS Programmable Logic |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MACH445-15YC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
| MACH445-20YC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
| MACH465-12YC | 制造商:Advanced Micro Devices 功能描述: |
| MACH465-20YC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACH4-96 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic |
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