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参数资料
| 型号： | MACH445-12YC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | High-Density EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 12 ns, PQFP100 |
| 封装： | PLASTIC, QFP-100 |
| 文件页数： | 27/28页 |
| 文件大小： | 214K |
| 代理商： | MACH445-12YC |
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27
MACH445-12/15/20
POWER-UP RESET
The MACH devices have been designed with the capa-
bility to reset during system power-up. Following power-
up, all flip-flops will be reset to LOW. The output state
will depend on the logic polarity. This feature provides
extra flexibility to the designer and is especially valuable
in simplifying state machine initialization. A timing dia-
gram and parameter table are shown below. Due to the
synchronous operation of the power-up reset and the
wide range of ways V
CC
can rise to its steady state, two
conditions are required to insure a valid power-up reset.
These conditions are:
1. The V
CC
rise must be monotonic.
2. Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter
Symbol
Parameter Descriptions
Max
Unit
t
PR
Power-Up Reset Time
10
μ
s
t
S
Input or Feedback Setup Time
t
WL
Clock Width LOW
See
Switching
Characteristics
t
PR
t
WL
t
S
4 V
V
CC
Power
Registered
Output
Clock
17468E-25
Power-Up Reset Waveform
相关PDF资料 |
PDF描述 |
|---|---|
| MACH445-15YC | High-Density EE CMOS Programmable Logic |
| MACH445-20YC | High-Density EE CMOS Programmable Logic |
| MACH5 | Fifth Generation MACH Architecture |
| MACHLV210-12 | High Density EE CMOS Programmable Logic |
| MACHLV210-12JC | High Density EE CMOS Programmable Logic |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MACH445-15YC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
| MACH445-20YC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
| MACH465-12YC | 制造商:Advanced Micro Devices 功能描述: |
| MACH465-20YC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACH4-96 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic |
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