DA9090B.001
January 14, 1998
24
REGISTER DESCRIPTION
Control register CR0
Master Clock Frequency Selection:
External MCLK frequency can be 512 kHz,
1.536 MHz, 2.048 MHz or 2.56 MHz. During
initialization Bits F1 (7) and F0 (6) must be set to
select correct value for internal clock divider. Default
value for external MCLK is 512 kHz. Any other value
must be selected before Power up command.
Coding Selection
Bit CM (5) permits selection of 14-bit linear coding
or companded coding. Default is linear mode.
In case of companded mode (CM=1) bits MA (4)
and IA (3) select either
μ
-255 or A law coding mode
and the format for both.
In case of linear mode (CM=0) bits MA (4) and IA
(3) select the linear data to be in 2’s complement,
1’s complement or sign and magnitude format.
Digital Interface Format (1)
Bit FF (2) selects the format for TX and Rx data
transfer. If FF=0 Format 1 is selected and channels
B1 and B2 are consecutive. FF = 1 selects Format 2
where channels B1 and B2 are separated by two
bits.
56+8 Selection (1)
If bit B7 (1) is selected MAS9090 takes only seven
most significant bits of the companded PCM data
byte. LSB bit on RX is ignored and LSB bit on TX is
in high impedance state. This allows direct
connection of an external “in band” data generator
to the digital interface.
Digital Loopback
Bit DL (0) selects the digital loopback mode, where
data written into RX data register (CR2) from
received time slot is read-back from that register in
the selected time-slot on TX.
No PCM decoding or encoding takes place in this
mode.
Control Register CR1
Digital Interface Timing
Bit TM1 (7) selects the timing mode for digital
interface. As a default (TM1=0) delayed timing
mode is selected. In delayed mode (TM1=1) bit
TM0 (6) selects the normal (TM0=0) or reversed
timing mode (TM0=1).
Latch output control
Bit DO (5) controls directly the LO output pin. Bit
written to DO is seen inverted from the output LO.
Microwire access on RX path (1)
When bit MR (4) is set high the data written into
register CR2 is decoded each frame and sent to
receive path. Data input RX is ignored when MR is
high.
In other direction, current PCM data input received
at RX can be read from register CR2 each frame.
Microwire access on TX path (1)
Bit MX (3) enables the access of write only register
CR3 to TX output. When MX is set active data
written to CR3 is send to TX output every frame.
PCM encoder is ignored.
Transmit/Receive enable/disable
Bit EN (2) enables or disables voice data transfer on
TX and RX pins. When disabled PCM data from RX
input is not decoded and TX output is on high
impedance state. Default value is disabled.
B-channel selection (1)
Bit TS (1) selects the active channel B1 or B2.
Default (TS=0) is B1 channel. (See Fig on page 14)
Power supply selection
Bit SV (0) selects the main supply voltage used.
When SV is low a 2.7-3.6 V supply is assumed.
When SV is high 4.5-5.5 V is expected.
Control Register CR2 (1)
Data sent to receive path or data received from RX
input is seen in register CR2. See register CR1 bit
MR (4).
Control Register CR3 (1)
TX data transmitted. Refer to bit MX (3) in CR1.
(1) Significant in companded mode only