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参数资料
| 型号： | MAX1035EUP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 16/31页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SER 115KSPS 20TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 位数： | 14 |
| 采样率（每秒）： | 115k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 879mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极；4 个单端，双极；2 个差分，单极；2 个差分，双极 |
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MAX1034/MAX1035
8-/4-Channel, ±VREF Multirange Inputs,
Serial 14-Bit ADCs
______________________________________________________________________________________
23
User supplies one byte of SCLK, then drives CS
high to relieve processor load while the ADC
converts
After SSTRB transitions high, the user supplies
two bytes of SCLK and reads data at DOUT
External Clock Mode (Mode 0)
The MAX1034/MAX1035’s fastest maximum throughput
rate is achieved operating in external clock mode.
SCLK controls both the acquisition and conversion of
the analog signal, facilitating precise control over when
the analog signal is captured. The analog input sam-
pling instant is at the falling edge of the 14th SCLK
(Figure 2).
Since SCLK drives the conversion in external clock
mode, the SCLK frequency should remain constant
while the conversion is clocked. The minimum SCLK
frequency prevents droop in the internal sampling
capacitor voltages during conversion.
SSTRB remains low in the external clock mode, and as a
result may be left unconnected if the MAX1034/
MAX1035 will always be used in the external clock mode.
External Acquisition Mode (Mode 1)
The slowest maximum throughput rate is achieved with
the external acquisition method. SCLK controls the acqui-
sition of the analog signal in external acquisition mode,
facilitating precise control over when the analog signal is
captured. The internal clock controls the conversion of
the analog input voltage. The analog input sampling
instant is at the falling edge of the 16th SCLK (Figure 3).
CS
SCLK
DIN
DOUT
18
START
SEL2
SEL1
SEL0
R2
R1
R0
DIF/SGL
tCL
tCP
tCH
tDV
tCSS
tDS
tDH
tCSH
tCSPW
tTR
18
START
M2
M1
M0
1
0
ANALOG INPUT CONFIGURATION BYTE
MODE CONTROL BYTE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 15. Analog Input Configuration Byte and Mode-Control Byte Timing
CS
SCLK
DOUT
tCSS
HIGH
IMPEDANCE
SSTRB
tSSCS
MSB
tDO
NOTE: SSTRB AND CS REMAIN LOW IN EXTERNAL CLOCK MODE (MODE 0).
Figure 16. DOUT and SSTRB Timing
Table 7. Mode-Control Byte
BIT NUMBER
BIT NAME
DESCRIPTION
7
START
Start Bit. The first logic 1 after
CS goes low defines the beginning of the mode-control byte.
6M2
5M1
4M0
Mode-Control Bits. M[2:0] select the mode of operation as shown in Table 8.
3
1
Bit 3 must be a logic 1 for the mode-control byte.
2
0
Bit 2 must be a logic 0 for the mode-control byte.
1
0
Bit 1 must be a logic 0 for the mode-control byte.
0
Bit 0 must be a logic 0 for the mode-control byte.
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