MAX1048BETX+T (Maxim) PDF资料下载 Datasheet(18/39 页)

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参数资料

型号：	MAX1048BETX+T
厂商：	Maxim Integrated Products
文件页数：	18/39页
文件大小：	0K
描述：	IC ADC/DAC 10BIT 36-TQFN-EP
产品培训模块：	Lead (SnPb) Finish for COTS Obsolescence Mitigation Program
标准包装：	2,500
类型：	ADC，DAC
分辨率（位）：	10 b
采样率（每秒）：	225k
数据接口：	串行
电压电源：	模拟和数字
电源电压：	4.75 V ~ 5.25 V
工作温度：	-40°C ~ 85°C
安装类型：	表面贴装
封装/外壳：	36-WFQFN 裸露焊盘
供应商设备封装：	36-TQFN 裸露焊盘（6x6）
包装：	带卷 (TR)

MAX1040/MAX1042/MAX1046/MAX1048

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________

Table 9 details the four scan modes available in the

ADC conversion register. All four scan modes allow

averaging as long as the AVGON bit, bit 4 in the

averaging register, is set to 1. Select scan mode 10 to

scan the same channel multiple times. Clock mode 11

disables averaging. For example, if AVGON = 1,

NAVG[1:0] = 00, NSCAN[1:0] = 11, and SCAN[1:0] =

10, 16 results are written to the FIFO, with each result

being the average of four conversions of channel N.

DAC Select Register

Write a command byte 0001XXXX to the DAC select

face and indicate that another word will follow. The last

4 bits of the DAC select register are don’t-care bits. The

word that follows the DAC select-register command

byte controls the DAC serial interface. See Table 17

and the

DAC Serial Interface section.

Reset Register

Write to the reset register (as shown in Table 11) to

clear the FIFO or reset all registers (excluding the DAC

and GPIO registers) to their default states. When the

RESET bit in the reset register is set to 0, the FIFO is

cleared. Set the RESET bit to one to return all the

device registers to their default power-up state. All reg-

isters power up in state 00000000, except for the setup

and REFSEL1 = 1). The DAC and GPIO registers are

not reset by writing to the reset register. Set the SLOW

bit to one to add a 15ns delay in the DOUT signal path

to provide a longer hold time. Writing a one to the

SLOW bit also clears the contents of the FIFO. Set the

FBGON bit to one to force the bias block and bandgap

reference to power up regardless of the state of the

DAC and activity of the ADC block. Setting the FBGON

bit high also removes the programmed wake-up delay

between conversions in clock modes 01 and 11.

Setting the FBGON bit high also clears the FIFO.

GPIO Command

Write a command byte to the GPIO command register

to configure, write, or read the GPIOs, as detailed in

Table 12.

Table 10. DAC Select Register

BIT

NAME

BIT

FUNCTION

—

7 (MSB)

Set to zero to select DAC select register.

—

Set to zero to select DAC select register.

—

Set to zero to select DAC select register.

—

Set to one to select DAC select register.

Don’t care.

Table 11. Reset Register

BIT

NAME

BIT

FUNCTION

—

7 (MSB)

Set to zero to select ADC reset register.

—

Set to zero to select ADC reset register.

—

Set to zero to select ADC reset register.

—

Set to zero to select ADC reset register.

—

Set to one to select ADC reset register.

RESET

Set to zero to clear the FIFO only. Set to

one to set the device in its power-on

condition.

SLOW

Set to one to turn on slow mode.

FBGON

0 (LSB)

Set to one to force internal bias block and

bandgap reference to be always powered

up.

Table 12. GPIO Command Register

BIT NAME

BIT

FUNCTION

—

7 (MSB)