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| 型号： | MAX1089ETA+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 13/15页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 150KSPS 8-TDFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 150k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 740µW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 80°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WDFN 裸露焊盘 |
| 供应商设备封装： | 8-TDFN-EP（3x3） |
| 包装： | 标准包装 |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
| 产品目录页面： | 1395 (CN2011-ZH PDF) |
| 其它名称： | MAX1089ETA+TDKR |
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
_______________________________________________________________________________________
7
Detailed Description
The MAX1086–MAX1089 analog-to-digital converters
(ADCs) use a successive-approximation conversion (SAR)
technique and an on-chip track-and-hold (T/H) structure to
convert an analog signal into a 10-bit digital result.
The serial interface provides easy interfacing to micro-
processors (Ps). Figure 3 shows the simplified internal
structure for the MAX1086/MAX1087 (2–channels, sin-
gle-ended) and the MAX1088/MAX1089 (1–channel,
true-differential).
True-Differential Analog Input Track/Hold
The equivalent circuit of Figure 4 shows the
MAX1086–MAX1089’s input architecture which is com-
posed of a T/H, input multiplexer, comparator, and
switched-capacitor DAC. The T/H enters its tracking
mode on the rising edge of CNVST. The positive input
capacitor is connected to AIN1 or AIN2 (MAX1086/
MAX1087) or AIN+ (MAX1088/MAX1089). The negative
input capacitor is connected to GND (MAX1086/
MAX1087) or AIN- (MAX1088/MAX1089). The T/H enters
its hold mode on the falling edge of CNVST and the dif-
ference between the sampled positive and negative
input voltages is converted. The time required for the T/H
to acquire an input signal is determined by how quickly
its input capacitance is charged. If the input signal’s
source impedance is high, the acquisition time length-
ens, and CNVST must be held high for a longer period of
time. The acquisition time, tACQ, is the maximum time
needed for the signal to be acquired, plus the power-up
time. It is calculated by the following equation:
tACQ = 7 x (RS + RIN) x 24pF + tPWR
Pin Description
NAME
PIN
MAX1086
MAX1087
MAX1088
MAX1089
FUNCTION
1VDD
VDD
Positive Supply Voltage. +2.7V to +3.6V (MAX1087/MAX1089); +4.75V to +5.25V
(MAX1086/MAX1088). Bypass with a 0.1F capacitor to GND.
2
AIN1
AIN+
Analog Input Channel 1 (MAX1086/MAX1087) or Positive Analog Input (MAX1088/MAX1089)
3
AIN2
AIN-
Analog Input Channel 2 (MAX1086/MAX1087) or Negative Analog Input (MAX1088/MAX1089)
4
GND
Ground
5
REF
External Reference Voltage Input. Sets the analog voltage range. Bypass with a 0.1F
capacitor to GND.
6
CNVST
Conversion Start. A rising edge powers-up the IC and places it in track mode. At the falling
edge of CNVST, the device enters hold mode and begins conversion. CNVST also selects the
input channel (MAX1086/MAX1087) or input polarity (MAX1088/MAX1089).
7
DOUT
Serial Data Output. DOUT transitions the falling edge of SCLK. DOUT goes low at the start of a
conversion and presents the MSB at the completion of a conversion. DOUT goes high-
impedance once data has been fully clocked out.
8
SCLK
Serial Clock Input. Clocks out data at DOUT MSB first.
—
EP
—
Exposed Pad (TDFN only). Connect the exposed pad to ground or leave unconnected.
10-BIT
SAR
ADC
CONTROL
OSCILLATOR
INPUT SHIFT
REGISTER
T/H
REF
CNVST
SCLK
DOUT
AIN2
(AIN-)
AIN1
(AIN+)
MAX1086–MAX1089
( ) ARE FOR MAX1088/MAX1089
Figure 3. Simplified Functional Diagram
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