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| 型号： | MAX1089ETA+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/15页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 150KSPS 8-TDFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 150k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 740µW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 80°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WDFN 裸露焊盘 |
| 供应商设备封装： | 8-TDFN-EP（3x3） |
| 包装： | 标准包装 |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
| 产品目录页面： | 1395 (CN2011-ZH PDF) |
| 其它名称： | MAX1089ETA+TDKR |
MAX1086–MAX1089
the first eight data bits starting with the MSB. The sec-
ond 8-bit data stream contains the remaining bits, D1
through D0, and the two sub-bits S1 and S0.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one starpoint (Figure 11), connecting the two ground
systems (analog and digital). For lowest-noise opera-
tion, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
High-frequency noise in the power supply (VDD) may
degrade the performance of the ADC’s fast comparator.
Bypass VDD to the star ground with a 0.1F capacitor,
located as close as possible to the MAX1086–MAX1089s
power supply pin. Minimize capacitor lead length for best
supply-noise rejection. Add an attenuation resistor (5
Ω) if
the power supply is extremely noisy.
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
12
______________________________________________________________________________________
CNVST
SCLK
DOUT
CS
SCK
MISO
VDD
SS
QSPI
MAX1086–
MAX1089
Figure 9a. QSPI Connections
Table 2. Detailed SSPSTAT Register Content
X = Don’t care
D/A
CONTROL BIT
MAX1086–MAX1089
SETTINGS
SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT)
Bit 5
X
Data Address Bit
P
Bit 4
X
Stop Bit
S
Bit 3
X
R/W
SMP
Bit 7
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.
CKE
Bit 6
1
SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
Bit 2
X
UA
Bit 1
X
BF
Bit 0
X
Start Bit
Buffer Full Status Bit
Update Address
Read/Write Bit Information
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
CNVST
1ST BYTE READ
SCLK
DOUT
2ND BYTE READ
SAMPLING INSTANT
4
18
12
B9
MSB
B8
B7
B6
B5
B4
B3
B2
B1
B0
LSB
S1
S0
HIGH-Z
16
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