参数资料
型号: MAX1110EVKIT
厂商: Maxim Integrated Products
文件页数: 16/20页
文件大小: 0K
描述: EVAL KIT FOR MAX1110
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
ADC 的数量: 1
位数: 8
采样率(每秒): 50k
数据接口: 串行
输入范围: 0 ~ VREF
在以下条件下的电源(标准): 0.23mW @ 50kSPS
工作温度: 0°C ~ 70°C
已用 IC / 零件: MAX1110,MAX1112
已供物品: 板,CD
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
_______________________________________________________________________________________
5
TIMING CHARACTERISTICS (Figures 8 and 9)
(VDD = 2.7V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.)
Note 1:
Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 2:
See
Typical Operating Characteristics.
Note 3:
VREFIN = 2.048V, offset nulled.
Note 4:
On-channel grounded; sine wave applied to all off-channels.
Note 5:
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:
Guaranteed by design. Not subject to production testing.
Note 7:
Common-mode range for the analog inputs is from AGND to VDD.
Note 8:
External load should not change during the conversion for specified accuracy.
Note 9:
External reference at 2.048V, full-scale input, 500kHz external clock.
Note 10: Measured as
| VFS (2.7V) - VFS (3.6V) |.
Note 11: 1F at REFOUT; internal reference settling to 0.5 LSB.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Track/Hold Acquisition Time
tACQ
1s
DIN to SCLK Setup
tDS
100
ns
DIN to SCLK Hold
tDH
0ns
SCLK Fall to Output Data Valid
tDO
Figure 1, CLOAD = 100pF
20
200
ns
CS Fall to Output Enable
tDV
Figure 1, CLOAD = 100pF
240
ns
CS Rise to Output Disable
tTR
Figure 2, CLOAD = 100pF
240
ns
CS to SCLK Rise Setup
tCSS
100
ns
CS to SCLK Rise Hold
tCSH
0ns
SCLK Pulse Width High
tCH
200
ns
SCLK Pulse Width Low
tCL
200
ns
SCLK Fall to SSTRB
tSSTRB
CLOAD = 100pF
240
ns
CS Fall to SSTRB Output Enable
(Note 6)
tSDV
Figure 1, external clock mode only,
CLOAD = 100pF
240
ns
CS Rise to SSTRB output
Disable (Note 6)
tSTR
Figure 2, external clock mode only,
CLOAD = 100pF
240
ns
SSTRB Rise to SCLK Rise
(Note 6)
tSCK
Figure 11, internal clock mode only
0
ns
External reference
20
s
Wake-Up Time
tWAKE
Internal reference (Note 11)
12
ms
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