参数资料
型号: MAX1110EVL11-DIP
厂商: Maxim Integrated Products
文件页数: 18/20页
文件大小: 0K
描述: EVAL KIT FOR MAX1110
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
ADC 的数量: 1
位数: 8
采样率(每秒): 50k
数据接口: 串行
输入范围: 0 ~ VREF
在以下条件下的电源(标准): 0.23mW @ 50kSPS
工作温度: 0°C ~ 70°C
已用 IC / 零件: MAX1110,MAX1112
已供物品: 2 板,CD
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
_______________________________________________________________________________________
7
______________________________________________________________Pin Description
16
SSTRB
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1110/
MAX1111 begin the A/D conversion and goes high when the conversion is done.
In external clock mode, SSTRB pulses high for two clock periods before the MSB is
shifted out. High impedance when CS is high (external clock mode only).
20
VDD
Positive Supply Voltage, 2.7V to 5.5V
18
CS
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is
high, DOUT is high impedance. The voltage at CS can exceed VDD (up to 5.5V).
19
SCLK
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode,
SCLK also sets the conversion speed (duty cycle must be 45% to 55%). The voltage at
SCLK can exceed VDD (up to 5.5V).
17
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge. The voltage at DIN can
exceed VDD (up to 5.5V).
12
REFOUT
Internal Reference Generator Output. Bypass with a 1F capacitor to AGND.
14
DGND
Digital Ground
15
DOUT
Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when
CS is high.
13
AGND
Analog Ground
10
SHDN
Three-Level Shutdown Input. Normally high impedance. Pulling SHDN low shuts the
MAX1110/MAX1111 down to 10A (max) supply current; otherwise, the devices are
fully operational. Pulling SHDN high shuts down the internal reference.
11
REFIN
Reference Voltage Input for Analog-to-Digital Conversion. Connect to REFOUT to use
the internal reference.
5–8
CH4–CH7
Sampling Analog Inputs
1–4
CH0–CH3
Sampling Analog Inputs
+3V
3k
Ω
CLOAD
DGND
DOUT
CLOAD
DGND
3k
Ω
DOUT
a) High-Z to VOH and VOL to VOH
b) High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Enable Time
+3V
3k
Ω
CLOAD
DGND
DOUT
CLOAD
DGND
3k
Ω
DOUT
a) VOH to High-Z
b) VOL to High-Z
Figure 2. Load Circuits for Disable Time
12
16
14
15
13
8
10
11
9
6
7
1–4
5
9
COM
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode.
Must be stable to ±0.5 LSB.
PIN
MAX1111
NAME
FUNCTION
MAX1110
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