参数资料
型号: MAX1112EAP+T
厂商: Maxim Integrated Products
文件页数: 18/20页
文件大小: 0K
描述: IC ADC 8BIT LP 20-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
位数: 8
采样率(每秒): 50k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 680µW
电压电源: 单电源
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 20-SSOP(0.209",5.30mm 宽)
供应商设备封装: 20-SSOP
包装: 带卷 (TR)
输入数目和类型: 8 个单端,单极;8 个单端,双极;4 个伪差分,单极;4 个伪差分,双极
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
_______________________________________________________________________________________
7
Pin Description
16
SSTRB
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1112/
MAX1113 begin the A/D conversion and goes high when the conversion is complete.
In external clock mode, SSTRB pulses high for two clock periods before the MSB is
shifted out. High impedance when CS is high (external clock mode only).
20
VDD
Positive Supply Voltage, 4.5V to 5.5V. Bypass to AGND with 0.1F and 1F capacitor
as close as possible to the device. Place the 0.1F capacitor closer to VP-P.
18
CS
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is
high, DOUT is high impedance.
19
SCLK
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode,
SCLK also sets the conversion speed (duty cycle must be 45% to 55%).
17
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
12
REFOUT
Internal Reference Generator Output. Bypass with a 1F capacitor to AGND.
14
DGND
Digital Ground
15
DOUT
Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when
CS is high.
13
AGND
Analog Ground
10
SHDN
Three-Level Shutdown Input. Normally high impedance. Pulling SHDN low shuts the
MAX1112/MAX1113 down to 10A (max) supply current; otherwise, the devices are
fully operational. Pulling SHDN high shuts down the internal reference.
11
REFIN
Reference Voltage Input for Analog-to-Digital Conversion. Connect to REFOUT to use
the internal reference.
5–8
CH4–CH7
Sampling Analog Inputs
1–4
CH0–CH3
Sampling Analog Inputs
+5V
3k
Ω
CLOAD
DGND
DOUT
CLOAD
DGND
3k
Ω
DOUT
a) High-Z to VOH and VOL to VOH
b) High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Enable Time
+5V
3k
Ω
CLOAD
DGND
DOUT
CLOAD
DGND
3k
Ω
DOUT
a) VOH to High-Z
b) VOL to High-Z
Figure 2. Load Circuits for Disable Time
12
16
14
15
13
8
10
11
9
6
7
1–4
5
9
COM
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode.
Must be stable to ±0.5 LSB.
PIN
MAX1113
NAME
FUNCTION
MAX1112
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