参数资料
型号: MAX11206EEE+T
厂商: Maxim Integrated Products
文件页数: 10/27页
文件大小: 0K
描述: IC ADC 20BIT 16QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 20
采样率(每秒): 480
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 667mW
电压电源: 模拟和数字,双 ±
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 带卷 (TR)
输入数目和类型: 1 个差分,单极;1 个差分,双极
18
Maxim Integrated
20-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
MAX11206/MAX11207
STAT1: Status Register
SYSOR: The system gain overrange bit, when set to 1, indicates that a system gain calibration was over range. The
SCGC calibration coefficient is maximum value of 1.9999999. This bit, when set to 1, indicates that the full-scale value
out of the converter is likely not available.
RATE[2:0]: The data rate bits indicate the conversion rate that corresponds to the result in the DATA register or the
rate that was used for calibration coefficient calculation. If the previous conversions were done at a different rate, the
RATE[2:0] bits indicate a rate different than the rate of the conversion in progress.
OR: The overrange bit, OR, is set to 1 to indicate the conversion result has exceeded the maximum value of the
converter and that the result has been clipped or limited to the maximum value. The OR bit is set to 0 to indicate the
conversion result is within the full-scale range of the device.
UR: The underrange bit, UR, is set to 1 to indicate the conversion result has exceeded the minimum value of the
converter and that the result has been clipped or limited to the minimum value. The UR bit is set to 0 to indicate the
conversion result is within the full-scale range of the device.
MSTAT: The measurement status bit, MSTAT is set to 1 when a signal measurement is in progress. When MSTAT = 1,
a conversion, self-calibration, or system calibration is in progress and indicates that the modulator is busy. When the
modulator is not converting, the MSTAT bit is set to 0.
RDY: The RDY ready bit is set to 1 to indicate that a conversion result is available. Reading the DATA register resets the
RDY bit to 0 only after another conversion has been initiated. If the DATA has not been read before another conversion
is initiated, the RDY bit remains 1; if the DATA is read before another conversion is initiated, the RDY bit resets to 0. If
the DATA for the previous conversion is read during a following conversion, the RDY bit is reset immediately after the
DATA read operation has completed.
Table 11. STAT1 Register (Read Only)
BIT
B7
B6
B5
B4
B3
B2
B1
B0
BIT NAME
SYSOR
RATE2
RATE1
RATE0
OR
UR
MSTAT
RDY
DEFAULT
0
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