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参数资料
| 型号： | MAX1127EGK |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | ADC |
| 英文描述： | Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs |
| 中文描述： | 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC68 |
| 封装： | 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68 |
| 文件页数： | 5/25页 |
| 文件大小： | 1661K |
| 代理商： | MAX1127EGK |
M
Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= 1.8V, OV
DD
= 1.8V, CV
DD
= 1.8V, GND = 0, external V
REFIO
= 1.24V,
INTREF
= AV
DD
, C
REFIO
to GND = 0.1μF,
f
CLK
= 65MHz (50% duty cycle), DT = 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25
°
C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PDALL = 0, all channels
active
257
295
PDALL = 0, all channels
active, DT = 1
257
PDALL = 0, 1 channel active
PDALL = 0, PD[3:0] = 1111
82
23
mA
AV
DD
Supply Current
I
AVDD
f
IN
=
19.3MHz at
-0.5dBFS
PDALL = 1, global power
down, PD[3:0] =1111, no
clock input
300
μA
PDALL = 0, all channels
active
56
65
PDALL = 0, all channels
active, DT = 1
72
PDALL = 0, 1 channel active
PDALL = 0, PD[3:0] = 1111
42
37
mA
OV
DD
Supply Current
I
OVDD
f
IN
=
19.3MHz at
-0.5dBFS
PDALL = 1, global power-
down, PD[3:0] =1111, no
clock input
375
μA
CV
DD
Supply Current
I
CVDD
CV
DD
is used only to bias ESD-protection
diodes on CLK input, Figure 2
0
mA
Power Dissipation
TIMING CHARACTERISTICS
(Note 6)
P
DISS
f
IN
= 19.3MHz at -0.5dBFS
563
648
mW
Data Valid to CLKOUT Rise/Fall
t
OD
f
CLK
= 65MHz, Figure 5 (Notes 6 and 7)
(t
SAMPLE
/
24)
- 0.15
t
SAMPLE
/
24
(t
SAMPLE
/
24)
+ 0.15
ns
CLKOUT Output Width High
t
CH
Figure 5
t
S AMP LE
/
12
ns
CLKOUT Output Width Low
t
CL
Figure 5
t
S AMP LE
/
12
ns
FRAME Rise to CLKOUT Rise
t
CF
Figure 4 (Note 7)
(t
SAMPLE
/
24)
- 0.15
t
SAMPLE
/
24
(
SAMPLE
/
24)
+ 0.15
ns
Sample CLK Rise to Frame Rise
t
SF
Figure 4 (Notes 7 and 8)
(t
SAMPLE
/
2)
+0.9
(t
SAMPLE
/
2)
+1.3
(t
SAMPLE
/
2)
+1.7
ns
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