参数资料
型号: MAX1143BCAP+T
厂商: Maxim Integrated Products
文件页数: 3/20页
文件大小: 0K
描述: IC ADC 14BIT 200KSPS 20-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
位数: 14
采样率(每秒): 200k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 640mW
电压电源: 模拟和数字
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 20-SSOP(0.209",5.30mm 宽)
供应商设备封装: 20-SSOP
包装: 带卷 (TR)
输入数目和类型: 1 个单端,单极;1 个单端,双极
MAX1142/MAX1143
14-Bit ADC, 200ksps, +5V Single-Supply
with Reference
______________________________________________________________________________________
11
In external clock mode, SSTRB is high-impedance
when
CS is high. In external clock mode, CS is normally
held low during the entire conversion. If
CS goes high
during the conversion, SCLK is ignored until
CS goes
low. This allows external clock mode to be used with 8-
bit bytes.
Internal Clock
In internal clock mode, the MAX1142/MAX1143 gener-
ates its own conversion clock. This frees the micro-
processor from the burden of running the SAR conver-
sion clock, and allows the conversion results to be read
back at the processor’s convenience, at any clock rate
up to 8MHz.
SSTRB goes low at the start of the conversion and goes
high when the conversion is complete. SSTRB will be
low for a maximum of 6s, during which time SCLK
should remain low for best noise performance. An inter-
nal register stores data when the conversion is in
progress. SCLK clocks the data out of the internal stor-
age register at any time after the conversion is com-
plete.
The MSB of the conversion is available at DOUT when
SSTRB goes high. The subsequent 15 falling edges on
SCLK shift the remaining bits out of the internal storage
register (Figure 4).
CS does not need to be held low
once a conversion is started.
When internal clock mode is selected, SSTRB does not
go into a high-impedance state when
CS goes high.
Figure 5 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted into
the MAX1142/MAX1143 at clock rates up to 4.8MHz,
provided that the minimum acquisition time,
tACQ, is kept above 1.14s in bipolar mode and 1.82s
in unipolar-mode. Data can be clocked out at 8MHz.
Output Data
The output data format is straight binary for unipolar
conversions and two’s complement in bipolar mode. In
both modes the MSB is shifted out of the MAX1142/
MAX1143 first.
Table 2. User-Programmable Outputs
OUTPUT
PIN
PROGRAMMED
THROUGH
CONTROL-
BYTE
POWER-ON
OR
RST
DEFAULT
DESCRIPTION
P2
Bit 2
0
P1
Bit 1
0
P0
Bit 0
0
User programmable outputs follow the state of the Control-Byte’s three LSBs,
and are updated simultaneously when a new Control-Byte is written. Outputs
are push-pull. In hardware and software shutdown, these outputs are
unchanged and remain low-impedance.
ACQUISITION
CONVERSION
IDLE
SCLK
DOUT
A/D
STATE
DIN
SSTRB
CS
4
1
8
12
START
M1
M0
P2
P1
P0
UNI/
BIP
INT/
EXT
15
21
24
B10
B9
B12
B11
B8
B7
B2
B13
MSB
B0
LSB
FILLED WITH
ZEROS
B1
X
tACQ
Figure 2. Short Acquisition Mode (24-Clock Cycles) External Clock, Bipolar Mode
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