参数资料
型号: MAX115CAX+T
厂商: Maxim Integrated Products
文件页数: 4/14页
文件大小: 0K
描述: IC DAS SYSTEM 12BIT 36-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1,000
类型: 数据采集系统(DAS)
分辨率(位): 12 b
数据接口: 并联
电压电源: 模拟和数字
电源电压: 4.75 V ~ 5.25 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 36-BSOP(0.295",7.50mm 宽)
供应商设备封装: 36-SSOP
包装: 带卷 (TR)
MAX115/MAX116
(LSB) values. Output coding is two-complement binary
with
1LSB
=
2.44mV
for
the
MAX115
and
1LSB = 1.22mV for the MAX116.
Output Demultiplexer
An output demultiplexer circuit is useful for isolating
data from one channel in a four-channel conversion
sequence. Figure 9’s circuit uses the external 16MHz
clock and the INT signal to generate four RD pulses
and a latch clock to save data from the desired chan-
nel. CS must be low during the four RD pulses. The
channel is selected with the binary coding of two
switches. A 16-bit 16373 latch simplifies layout.
Motor-Control Applications
Vector motor control requires monitoring of the individ-
ual phase currents. In their most basic application, the
MAX115/MAX116 simultaneously sample two currents
(CH1A and CH2A, Figure 10) and preserve the neces-
sary relative phase information. Only two of the three
phase currents have to be digitized because the third
component can be mathematically derived with a coor-
dinate transformation.
The circuit of Figure 10 shows a typical vector motor-
control application using all available inputs of the
MAX115/MAX116. CH1A and CH2A are connected
to two isolated Hall-effect current sensors and are a
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
12
______________________________________________________________________________________
PRE
CLR
HC161
1/2 HC74
VCC
ENP
ENT
LOAD
A
B
C
D
(LSB) 0
1
2
3
RCO
DQ
Q
CLR
P0
P1
P2
P3
P4
P5
P6
P7
HC688
P = Q
Q0
Q1
Q2
VCC
Q3
Q4
Q5
Q6
Q7
G
LATCH
CLOCK
(TO 16373 LATCH)
0
CH1
0
1
CH2
0
CH3
1
CH4
1
10k
EXTERNAL
CLOCK
EXTERNAL
CLOCK
RD
INT
Figure 9. Output Demultiplexer Circuit
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