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参数资料
| 型号： | MAX115CAX+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/14页 |
| 文件大小： | 0K |
| 描述： | IC DAS SYSTEM 12BIT 36-SSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 类型： | 数据采集系统（DAS） |
| 分辨率（位）： | 12 b |
| 数据接口： | 并联 |
| 电压电源： | 模拟和数字 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-BSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 36-SSOP |
| 包装： | 带卷 (TR) |
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
4
_______________________________________________________________________________________
CONDITIONS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
IOUT = 1mA
V
4
VOH
Output High Voltage
IOUT = -1.6mA
V
0.4
VOL
Output Low Voltage
D0–D11
A
±10
Three-State Leakage Current
pF
10
Three-State Output
Capacitance
V
4.75
5
5.25
AVDD
Positive Supply Voltage
V
-5.25
-5
-4.75
AVSS
Negative Supply Voltage
V
4.75
5
5.25
DVDD
Digital Supply Voltage
mA
17
25
IAVDD
Positive Supply Current
mA
-20
-15
IAVSS
Negative Supply Current
mA
36
Digital Supply Current
A
1
Shutdown Positive Current
A
-1
Shutdown Negative Current
A
13
Shutdown Digital Current
(Note 10)
LSB
±1
PSRR+
Positive Supply Rejection
(Note 10)
LSB
±1
PSRR-
Negative Supply Rejection
(Note 11)
mW
175
Power Dissipation
DIGITAL OUTPUTS (D0–D11, INT)
POWER REQUIREMENTS
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +5V ±5%, AVSS = -5V ±5%, DVDD = +5V ±5%, VREFIN = +2.5V (external reference), AGND = DGND = 0, 4.7F capacitor
from REFOUT to AGND, 0.1F capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle. TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
TIMING CHARACTERISTICS
(See Figure 4, AVDD = +5V, AVSS = -5V, DVDD = +5V, AGND = DGND = 0, TA = TMIN to TMAX, Typical values are at TA = +25°C,
unless otherwise noted.)
Guaranteed by design
ns
0
tCWS
CS to WR Setup Time
Guaranteed by design
ns
0
tCWH
CS to WR Hold Time
ns
30
tWR
WR Low Pulse Width
ns
30
CONDITIONS
tAS
Address Setup Time
ns
0
tAH
Address Hold Time
25pF load
ns
55
tID
RD to INT Delay
ns
45
tRD
Delay Time Between Reads
Guaranteed by design
ns
0
tCRS
CS to RD Setup Time
Guaranteed by design
ns
0
tCRH
CS to RD Hold Time
ns
30
tRD
RD Low Pulse Width
25pF load (Note 12)
ns
40
tDA
Data-Access Time
25pF load (Note 13)
ns
545
tDH
Bus-Relinquish Time
ns
30
tCW
CONVST Pulse Width
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
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