参数资料
型号: MAX11647EUA+T
厂商: Maxim Integrated Products
文件页数: 3/22页
文件大小: 0K
描述: IC ADC 10BIT I2C 94.4KSPS 8UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 10
采样率(每秒): 94.4k
数据接口: I²C,串行
转换器数目: 1
功率耗散(最大): 362mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-uMAX
包装: 带卷 (TR)
输入数目和类型: 2 个单端,单极;2 个单端,双极;1 个差分,单极;1 个差分,双极
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
______________________________________________________________________________________
11
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
0V within the limits of 10-bit resolution. This action
requires 10 conversion clock cycles and is equivalent
to transferring a charge of 11pF (VIN+ - VIN-) from
CT/H to the binary-weighted capacitive DAC, forming a
digital representation of the analog input signal.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of up to 1.5k
Ω
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source impedances,
connect a 100pF capacitor from the analog input to GND.
This input capacitor forms an RC filter with the source
impedance limiting the analog-input bandwidth. For larg-
er source impedances, use a buffer amplifier to maintain
analog-input signal integrity and bandwidth.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the eighth rising clock edge
of the address byte (see the
Slave Address section). The
T/H circuitry enters hold mode on the falling clock edge of
the acknowledge bit of the address byte (the ninth clock
pulse). A conversion or a series of conversions is then
internally clocked and the MAX11646/MAX11647 hold
SCL low. With external clock mode, the T/H circuitry
enters track mode after a valid address on the rising
edge of the clock during the read (R/W = 1) bit. Hold
mode is then entered on the rising edge of the second
clock pulse during the shifting out of the first byte of the
result. The conversion is performed during the next 10
clock cycles.
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capaci-
tance. If the analog input source impedance is high,
the acquisition time constant lengthens and more time
must be allowed between conversions. The acquisition
time (tACQ) is the minimum time needed for the signal
to be acquired. It is calculated by:
tACQ
≥ 9 (RSOURCE + RIN) CIN
where RSOURCE is the analog input source impedance,
RIN = 2.5k
Ω, and CIN = 22pF. tACQ is 1.5/fSCL for internal
clock mode and tACQ = 2/fSCL for external clock mode.
Analog Input Bandwidth
The MAX11646/MAX11647 feature input-tracking cir-
cuitry with a 5MHz small-signal bandwidth. The 5MHz
input bandwidth makes it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using under sampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Range and Protection
Internal protection diodes clamp the analog input to
VDD and GND. These diodes allow the analog inputs to
swing from (VGND - 0.3V) to (VDD + 0.3V) without caus-
ing damage to the device. For accurate conversions
the inputs must not go more than 50mV below GND or
above VDD.
TRACK
HOLD
CT/H
TRACK
HOLD
AIN0
AIN1
GND
ANALOG INPUT MUX
CAPACITIVE
DAC
REF
CAPACITIVE
DAC
REF
MAX11646
MAX11647
HOLD
TRACK
HOLD
VDD/2
Figure 4. Equivalent Input Circuit
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