参数资料
型号: MAX11647EUA+T
厂商: Maxim Integrated Products
文件页数: 9/22页
文件大小: 0K
描述: IC ADC 10BIT I2C 94.4KSPS 8UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 10
采样率(每秒): 94.4k
数据接口: I²C,串行
转换器数目: 1
功率耗散(最大): 362mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-uMAX
包装: 带卷 (TR)
输入数目和类型: 2 个单端,单极;2 个单端,双极;1 个差分,单极;1 个差分,双极
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
______________________________________________________________________________________
17
External Clock
When configured for external clock mode (CLK = 1),
the MAX11646/MAX11647 use the SCL as the conver-
sion clock. In external clock mode, the MAX11646/
MAX11647 begin tracking the analog input on the ninth
rising clock edge of a valid slave address byte. Two
SCL clock cycles later the analog signal is acquired
and the conversion begins. Unlike internal clock mode,
converted data is available immediately after the first
four empty high bits. The device continuously converts
input channels dictated by the scan mode until given a
not acknowledge. There is no need to re-address the
device with a read command to obtain new conversion
results (see Figure 11).
The conversion must complete in 1ms or droop on the
track-and-hold capacitor degrades conversion results.
Use internal clock mode if the SCL clock period
exceeds 60s.
The MAX11646/MAX11647 must operate in external
clock mode for conversion rates from 40ksps to
94.4ksps. Below 40ksps internal clock mode is recom-
mended due to much smaller power consumption.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan mode configuration. Table 5 shows the scanning
configurations. The scanned results are written to mem-
ory in the same order as the conversion. Read the
results from memory in the order they were converted.
Each result needs a 2-byte transmission, the first byte
begins with six empty bits during which SDA is left
high. Each byte has to be acknowledged by the master
or the memory transmission is terminated. It is not pos-
sible to read the memory independently of conversion.
SLAVE ADDRESS
tCONV1
tACQ1
tACQ2
tCONVN
tACQN
tCONV
tACQ
NUMBER OF BITS
1
8
A
1
S
1
A
71 1
R
S
1
71 1
R
P OR Sr
1
8
A
1
A
8
A
8
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
SLAVE ADDRESS
P OR Sr
RESULT (8 LSBs)
8
A
1
RESULT (2 MSBs)
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
RESULT 1 (2 MSBs)
RESULT 2 (8 LSBs)
RESULT N (8 LSBs)
A
1
8
RESULT N (2 MSBs)
A
Figure 11. External Clock Mode Read Cycle
SCAN1
SCAN0
SCANNING CONFIGURATION
0
Scans up from AIN0 to the input selected by CS0.
0
1
Converts the input selected by CS0 eight times (see Tables 3 and 4).*
1
0
Reserved. Do not use.
1
Converts input selected by CS0.*
*
When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11, and converting occurs
perpetually until not acknowledge occurs.
Table 5. Scanning Configuration
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