参数资料
型号: MAX1168AEEG
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: ADC
英文描述: Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters
中文描述: 8-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
封装: 0.150 INCH, 0.025 INCH PITCH, MO-137AE, QSOP-24
文件页数: 18/30页
文件大小: 462K
代理商: MAX1168AEEG
M
The MAX1168 external clock 16-bit-wide data-transfer
mode requires 32 SCLK cycles for completion (Figure 11).
Force
CS
high after the conversion result is read. For
maximum throughput, force
CS
low again to initiate the
next conversion immediately after the specified mini-
mum time (t
CSW
). Forcing
CS
high in the middle of a
conversion immediately aborts the conversion and
places the MAX1168 in shutdown.
Internal Clock 8-Bit-Wide Data-Transfer and
Scan Mode (MAX1167 and MAX1168)
Force DSPR high and DSEL low (MAX1168) for the SPI/
QSPI/MICROWIRE interface mode. The falling edge of
CS
wakes the analog circuitry and allows SCLK to clock
in data (Figure 12). DOUT changes from high-Z to logic
low after
CS
is brought low. Input data latches on the ris-
ing edge of SCLK. The command/configuration/control
register begins reading DIN on the first SCLK rising edge
and ends on the rising edge of the 8th SCLK cycle. The
MAX1167/MAX1168 select the proper channel for con-
version on the rising edge of the 3rd SCLK cycle. The
internal oscillator activates 125ns after the rising edge of
the 8th SCLK cycle. Turn off the external clock while the
internal clock is on. Turning off SCLK ensures the lowest
noise performance during acquisition. Acquisition begins
on the 2nd rising edge of the internal clock and ends on
the falling edge of the 6th internal clock cycle. Each bit
of the conversion result shifts into memory as it becomes
available. The conversion result is available (MSB first) at
DOUT on the falling edge of
EOC
. The internal oscillator
and analog circuitry are shut down on the high-to-low
EOC
transition. Use the
EOC
high-to-low transition as the
signal to restart the external clock (SCLK). To read the
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
18
______________________________________________________________________________________
DOUT
CS
SCLK
DIN
DSPR
0
MSB
LSB
MSB
LSB
ADC
STATE
16
24
32
1
8
X
X
X
X
X
X
X
X
X = DON,T CARE
t
ACQ
IDLE
t
CONV
DSEL
Figure 11. SPI External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
DOUT
CS
SCLK
DIN
EOC
1
MSB
LSB
LSB
X
t
ACQ
IDLE
t
CONV
POWER-DOWN
ADC
STATE
X = DON,T CARE
DSPR = DV
DD
, DSEL = GND (MAX1168 ONLY)
Figure 12. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing
INTERNAL
CLK
1
8
2
6
25
16
9
24
MSB
相关PDF资料
PDF描述
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相关代理商/技术参数
参数描述
MAX1168AEEG+ 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
MAX1168AEEG+T 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
MAX1168AEEG-T 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
MAX1168BCEG 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
MAX1168BCEG+ 功能描述:模数转换器 - ADC 16-Bit 8Ch 200ksps 5.25V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32