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参数资料
| 型号： | MAX1168AEEG |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | ADC |
| 英文描述： | Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters |
| 中文描述： | 8-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封装： | 0.150 INCH, 0.025 INCH PITCH, MO-137AE, QSOP-24 |
| 文件页数： | 22/30页 |
| 文件大小： | 462K |
| 代理商： | MAX1168AEEG |
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M
setting bits 4 and 3 in the command/configuration/con-
trol register (see Tables 3 and 4). In scan mode, conver-
sion results are stored in memory until the completion of
the last conversion in the sequence. Upon completion of
the last conversion in the sequence,
EOC
transitions
from high to low to indicate the end of the conversion
and shuts down the internal oscillator. Use the
EOC
high-to-low transition as the signal to restart the external
clock (SCLK). DOUT provides the conversion results in
the same order as the channel conversion process. The
MSB of the first conversion is available at DOUT on the
falling edge of
EOC
. Figure 15 shows the timing
diagram for 16-bit-wide data transfer in scan mode.
DSP 8-Bit-Wide Data-Transfer Mode (External Clock
Mode, MAX1168 Only)
Figure 16 shows the DSP-interface timing diagram.
Logic low at DSPR on the falling edge of
CS
enables
DSP interface mode. After the MAX1168 enters DSP
mode,
CS
can remain low for the duration of the conver-
sion process and each subsequent conversion. Drive
DSEL low to select the 8-bit data-transfer mode. A sync
pulse from the DSP at DSPR wakes the analog circuitry
and allows SCLK to clock in data (Figure 17). The frame
sync pulse alerts the MAX1168 that incoming data is
about to be sent to DIN. Ensure the duty cycle on SCLK
is between 45% and 55% when operating at 4.8MHz
(the maximum clock frequency). For lower clock fre-
quencies, ensure the minimum high and low times are at
least 93ns. External clock mode conversions with SCLK
rates less than 125kHz can reduce accuracy due to
leakage of the sampling capacitor. The input data
latches on the falling edge of SCLK. The command/
configuration/control register starts reading data in on
the falling edge of the first SCLK cycle immediately fol-
lowing the falling edge of the frame sync pulse and
ends on the falling edge of the 8th SCLK cycle. The
MAX1168 selects the proper channel for conversion on
the falling edge of the 3rd clock cycle and begins
acquisition. Acquisition continues until the rising edge
of the 7th clock cycle. The MAX1168 samples the input
on the rising edge of the 7th clock cycle. On the rising
edge of the 8th clock cycle, the MAX1168 outputs a
frame sync pulse at DSPX. The frame sync pulse alerts
the DSP that the conversion results are about to be out-
put at DOUT (MSB first) starting on the rising edge of
the 9th clock pulse. To read the entire conversion
result, 16 SCLK cycles are needed. Extra clock pulses,
occurring after the conversion result has been clocked
out and prior to the next rising edge of DSPR, cause
zeros to be clocked out of DOUT. The MAX1168 exter-
nal clock, DSP 8-bit-wide data-transfer mode requires
24 clock cycles to complete.
Begin a new conversion by sending a new frame sync
pulse to DSPR followed by new configuration data.
Send the new DSPR pulse immediately after reading
the conversion result to realize maximum throughput.
Sending a new frame sync pulse in the middle of a con-
version immediately aborts the current conversion and
begins a new one. A rising edge on
CS
in the middle of
a conversion aborts the current conversion and places
the MAX1168 in shutdown.
DSP 16-Bit-Wide Data-Transfer Mode (External
Clock Mode, MAX1168 Only)
Figure 16 shows the DSP-interface timing diagram.
Logic low at DSPR on the falling edge of
CS
enables
DSP interface mode. After the MAX1168 enters DSP
mode,
CS
can remain low for the duration of the con-
version process and each subsequent conversion. The
acquisition time is extended an extra eight SCLK cycles
in the 16-bit-wide data-transfer mode. Drive DSEL high
to select the 16-bit-wide data-transfer mode. A sync
pulse from the DSP at DSPR wakes the analog circuitry
and allows SCLK to clock in data (Figure 18). The
frame sync pulse also alerts the MAX1168 that incom-
ing data is about to be sent to DIN. Ensure the duty
cycle on SCLK is between 45% and 55% when operat-
ing at 4.8MHz (the maximum clock frequency). For
lower clock frequencies, ensure the minimum high and
low times are at least 93ns. External-clock-mode con-
versions with SCLK rates less than 125kHz can reduce
accuracy due to leakage of the sampling capacitor.
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
22
______________________________________________________________________________________
OUTPUT CODE
FULL-SCALE
TRANSITION
1111...111
1111...110
1111...101
1
2
3
0
FS
FS - 3/2 LSB
FS = V
REF
1 LSB = V
REF
INPUT VOLTAGE (LSB)
65,536
0000...011
0000...010
0000...001
0000...000
Figure 19. Unipolar Transfer Function, Full Scale (FS) = V
REF
,
Zero Scale (ZS) = GND
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1168AEEG+ | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1168AEEG+T | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1168AEEG-T | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1168BCEG | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1168BCEG+ | 功能描述:模数转换器 - ADC 16-Bit 8Ch 200ksps 5.25V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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