参数资料
型号: MAX1169CEUD+
厂商: Maxim Integrated Products
文件页数: 16/20页
文件大小: 0K
描述: IC ADC 16BIT 58.6KSPS 14-TSSOP
标准包装: 96
位数: 16
采样率(每秒): 58.6k
数据接口: I²C,串行
转换器数目: 1
功率耗散(最大): 864mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 14-TSSOP
包装: 管件
输入数目和类型: 8 个单端,单极
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
_______________________________________________________________________________________
5
Note 1: DC accuracy is tested at VAVDD = +5.0V and VDVDD = +3.0V. Performance at power-supply tolerance limits is guaranteed
by power-supply rejection test.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3: Offset nullified.
Note 4: One sample is achieved every 18 clocks in continuous conversion mode:
Note 5: The track/hold acquisition time is two SCL cycles as illustrated in Figure 11:
Note 6: A filter on SDA and SCL delays the sampling instant and suppresses noise spikes less than 10ns in high-speed mode and
50ns in fast mode.
Note 7: ADC performance is limited by the converter’s noise floor, typically 225μVP-P.
Note 8:
PSRR
V
(5.25V)-V
(4.75V)
2
V
5.25V
FS
N
REF
=
×
-- 4.75V
where N is the number of bits (
).
16
t2
1
f
ACQ
SCL
f
1 clocks
f
t
SAMPLE
SCL
C
-1
=+
8
ONV
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external
reference applied to REF, REFADJ = AVDD, CREF = 10μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figure 1b and Figure 2)
Serial Clock Frequency
fSCLH
(Note 11)
1.7
MHz
Hold Time (Repeated) Start
Condition
tHD, STA
160
ns
Low Period of the SCL Clock
tLOW
320
ns
High Period of the SCL Clock
tHIGH
120
ns
Setup Time for a Repeated
START Condition
tSU, STA
160
ns
Data Hold Time
tHD, DAT
(Note 9)
0
150
ns
Data Setup Time
tSU, DAT
10
ns
Rise Time of SCL Signal
(Current Source Enabled)
tRCL
(Note 10)
10
80
ns
Rise Time of SCL Signal After
Acknowledge Bit
tRCL1
(Note 10)
20
160
ns
Fall Time of SCL Signal
tFCL
(Note 10)
20
80
ns
Rise Time of SDA Signal
tRDA
(Note 10)
20
160
ns
Fall Time of SDA Signal
tFDA
(Note 10)
20
160
ns
Setup Time for STOP Condition
tSU, STO
160
ns
Capacitive Load for Each Bus
CB
400
pF
Pulse Width of Spike Suppressed
tSP
10
ns
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