参数资料
型号: MAX1192ETI+T
厂商: Maxim Integrated Products
文件页数: 24/27页
文件大小: 0K
描述: IC ADC 8BIT 22MSPS DL 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 8
采样率(每秒): 22M
数据接口: 并联
转换器数目: 2
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
输入数目和类型: 4 个单端,双极;2 个差分,双极
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
6
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL
≈ 10pF at digital outputs, fCLK = 22MHz, CREFP = CREFN = CCOM =
0.33F, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
Note 1: Specifications
≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dB FS referenced to the
amplitude of the digital output. SNR and THD are calculated using HD2 through HD6.
Note 3: The power consumption of the output driver is proportional to the load capacitance (CL).
Note 4: Guaranteed by design and characterization. Not production tested.
Note 5: SINAD settles to within 0.5dB of its typical value.
Note 6: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the
second channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second
channel FFT test tone bins.
Note 7: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and
phase of the fundamental bin on the calculated FFT.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
tDOA
50% of CLK to 50% of data,
Figure 5 (Note 4)
1
6
8.5
ns
CLK Fall to CHB Output Data
Valid
tDOB
50% of CLK to 50% of data,
Figure 5 (Note 4)
1
6
8.5
ns
CLK Rise/Fall to A/
B Rise/Fall
Time
tDA/B
50% of CLK to 50% of A/
B,
Figure 5 (Note 4)
1
6
8.5
ns
PD1 Rise to Output Enable
tEN
PD0 = OVDD
5ns
PD1 Fall to Output Disable
tDIS
PD0 = OVDD
5ns
CLK Duty Cycle
50
%
CLK Duty Cycle Variation
±10
%
Wake-Up Time from Shutdown
Mode
tWAKE, SD (Note 5)
20
s
Wake-Up Time from Standby
Mode
tWAKE, ST (Note 5)
5.4
s
Digital Output Rise/Fall Time
20% to 80%
2
ns
INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection
fIN,X = 5.5MHz at -0.5dB FS,
fIN,Y = 0.3MHz at -0.5dB FS (Note 6)
-75
dB
Amplitude Matching
fIN = 5.5MHz at -0.5dB FS (Note 7)
±0.03
dB
Phase Matching
fIN = 5.5MHz at -0.5dB FS (Note 7)
±0.1
Degrees
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