参数资料
型号: MAX1202EVKIT
厂商: Maxim Integrated Products
文件页数: 23/24页
文件大小: 0K
描述: EVALUATION KIT FOR MAX1202
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
ADC 的数量: 1
位数: 12
采样率(每秒): 133k
数据接口: 串行
输入范围: ±VREF/2
在以下条件下的电源(标准): 7.5mW @ 133kSPS
工作温度: 0°C ~ 70°C
已用 IC / 零件: MAX1202,MAX1203
已供物品: 板,CD
______________________________________________________________Pin Description
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
8
_______________________________________________________________________________________
-1.0
-0.8
-0.6
-0.4
0
INTEGRAL NONLINEARITY
vs. DIGITAL
1.0
0.4
0.6
0.8
MAX1202
TOC09
DIGITAL CODE
INL
(LSB)
3000
0
-0.2
750
1500
2250
0.2
3750
4500
-120
0
FFT PLOT
20
MAX1202
TOC10
FREQUENCY (kHz)
AMPLITUDE
(dB)
-20
-40
-60
-80
-100
33.25
0
66.50
VSS = -5V
____________________________Typical Operating Characteristics (continued)
(VDD = 5V ±5%; VL = 2.7V to 3.6V; VSS = 0V; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle
(133ksps); MAX1202—4.7F capacitor at REF pin; MAX1203—external reference, VREF = 4.096V applied to REF pin; TA = +25°C;
unless otherwise noted.)
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1202/MAX1203 begin
the analog-to-digital conversion, and goes high when the conversion is finished. In external clock
mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS
is high (external clock mode).
SSTRB
16
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
DIN
17
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
CS
18
Serial-Clock Input. SCLK clocks data in and out of the serial interface. In external clock mode, SCLK
also sets the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
SCLK
19
Positive Supply Voltage, +5V ±5%
VDD
20
Input to the Reference-Buffer Amplifier. Tie REFADJ to VDD to disable the reference-buffer amplifier.
REFADJ
12
Ground; IN- Input for Single-Ended Conversions
GND
13
Supply Voltage for Digital Output Pins. Voltage applied to VL determines the positive output swing of
the Digital Outputs (DOUT, SSTRB). 2.7V
≤ VL ≤ 5.25V.
VL
14
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
DOUT
15
Reference-Buffer Output/ADC Reference Input. In internal reference mode (MAX1202 only), the refer-
ence buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference
mode, disable the internal buffer by pulling REFADJ to VDD.
REF
11
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1202/MAX1203 down to 10A (max)
supply current; otherwise, the MAX1202/MAX1203 are fully operational. Pulling SHDN to VDD puts the
reference-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference-
buffer amplifier in external compensation mode.
SHDN
10
PIN
Negative Supply Voltage. Tie VSS to -5V ±5% or to GND.
VSS
9
Sampling Analog Inputs
CH0–CH7
1–8
FUNCTION
NAME
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