参数资料
型号: MAX1202EVKIT
厂商: Maxim Integrated Products
文件页数: 4/24页
文件大小: 0K
描述: EVALUATION KIT FOR MAX1202
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
ADC 的数量: 1
位数: 12
采样率(每秒): 133k
数据接口: 串行
输入范围: ±VREF/2
在以下条件下的电源(标准): 7.5mW @ 133kSPS
工作温度: 0°C ~ 70°C
已用 IC / 零件: MAX1202,MAX1203
已供物品: 板,CD
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
12
______________________________________________________________________________________
Table 2. Control-Byte Format
Table 3. Channel Selection in Single-Ended Mode (SGL/D
DIIF
F = 1)
SEL1
SEL0
0
CH4
CH5
SEL2
CH6
CH7
GND
1
0
+
0
1
+
1
0
CH0
+
1
+
0
1
CH1
0
+
1
CH3
0
+
0
1
CH2
1
+
1
+
Table 4. Channel Selection in Differential Mode (SGL/D
DIIF
F = 0)
SEL1
SEL0
0
CH4
CH5
SEL2
CH6
CH7
0
1
+
0
1
0
+
0
1
CH0
+
1
+
1
0
CH1
0
+
1
0
CH3
1
+
1
CH2
0
+
1
+
PD0
Bit 0
(LSB)
SGL/DIF
Bit 2
PD1
Bit 1
UNI/BIP
Bit 3
SEL 0
Bit 4
Bit 7
(MSB)
SEL 1
SEL 2
START
Bit 5
Bit 6
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF / 2 to +VREF / 2.
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to GND. In differential mode, the voltage dif-
ference between two channels is measured. (Tables 3 and 4.)
Selects clock and power-down modes.
PD1
PD0
Mode
00
Full power-down (IDD = 2A, internal reference)
01
Fast power-down (IDD = 30A, internal reference)
10
Internal clock mode
11
External clock mode
These three bits select which of the eight channels is used for the conversion
(Tables 3 and 4).
The first logic 1 bit after CS goes low defines the beginning of the control byte.
UNI/BIP
3
SGL/DIF
2
PD1
PD0
1
0 (LSB)
SEL2
SEL1
SEL0
6
5
4
START
7 (MSB)
Description
Name
Bit
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