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| 型号： | MAX1203BEAP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 21/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 8CH 20-SSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 位数： | 12 |
| 采样率（每秒）： | 133k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 7.5mW |
| 电压电源： | 双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 8 个单端，单极；8 个单端，双极；4 个差分，单极；4 个差分，双极 |
MAX1202/MAX1203
5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(VDD = +5V ±5%, VL = 2.7V to 3.6V, VSS = 0V or -5V ±5%, TA = TMIN to TMAX, unless otherwise noted.)
Note 1:
Tested at VDD = 5.0V; VSS = 0V; unipolar-input mode.
Note 2:
Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 3:
MAX1202—internal reference, offset nulled; MAX1203—external reference (VREF = 4.096V), offset nulled.
Note 4:
On-channel grounded; sine wave applied to all off-channels.
Note 5:
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:
Guaranteed by design. Not subject to production testing.
Note 7:
Common-mode range for analog inputs is from VSS to VDD.
Note 8:
External load should not change during the conversion for specified accuracy.
Note 9:
Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND;
REFADJ = GND. Shutdown supply current is also dependent on VIH (Figure 12c).
Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are
active (CS low), the logic supply current depends on fSCLK, and on the static and capacitive load at DOUT and SSTRB.
Note 11: Measured at VSUPPLY + 5% and VSUPPLY - 5% only.
Note 12: Measured at VL = 2.7V and VL = 3.6V.
ns
100
tCSS
External-clock mode only, CLOAD = 100pF
ns
CS to SCLK Rise Setup
240
CLOAD = 100pF
ns
20
240
ns
0
tDO
SCLK Fall to Output Data Valid
tCSH
CONDITIONS
CS to SCLK Rise Hold
240
tDV
CS Fall to Output Enable
CLOAD = 100pF
ns
240
tTR
CS Rise to Output Disable
tSDV
CS Fall to SSTRB Output Enable
(Note 6)
External-clock mode only, CLOAD = 100pF
ns
240
tSTR
CS Rise to SSTRB Output
Disable (Note 6)
Internal-clock mode only
ns
0
tSCK
SSTRB Rise to SCLK Rise
(Note 6)
ns
200
tCH
SCLK Pulse Width High
ns
200
tCL
SCLK Pulse Width Low
CLOAD = 100pF
ns
240
tSSTRB
SCLK Fall to SSTRB
CLOAD = 100pF
ns
0
tDH
DIN to SCLK Hold
s
1.5
tACQ
Acquisition Time
ns
100
tDS
DIN to SCLK Setup
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
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