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参数资料
| 型号： | MAX1246EVKIT |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/25页 |
| 文件大小： | 0K |
| 描述： | EVALUATION KIT FOR MAX1246 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 133k |
| 数据接口： | 串行 |
| 输入范围： | ±VREF/2 |
| 在以下条件下的电源（标准）： | 3.6mW @ 133kSPS |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | MAX1246 |
| 已供物品： | 板，CD |
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
16
______________________________________________________________________________________
__________ Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1246/MAX1247 in internal clock mode, ready to
convert with SSTRB = high. After the power supplies
stabilize, the internal reset time is 10s, and no conver-
sions should be performed during this phase. SSTRB is
high on power-up and, if CS is low, the first logical 1 on
DIN is interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros. (Also see Table 4.)
Reference-Buffer Compensation
In addition to its shutdown function, SHDN selects inter-
nal or external compensation. The compensation
affects both power-up time and maximum conversion
speed. The100kHz minimum clock rate is limited by
droop on the sample-and-hold and is independent of
the compensation used.
Float SHDN to select external compensation. The
Typical Operating Circuit uses a 4.7F capacitor at
VREF. A 4.7F value ensures reference-buffer stability
and allows converter operation at the 2MHz full clock
speed. External compensation increases power-up
time (see the Choosing Power-Down Mode section and
Table 4).
Pull SHDN high to select internal compensation.
Internal compensation requires no external capacitor at
VREF and allows for the shortest power-up times. The
maximum clock rate is 2MHz in internal clock mode
and 400kHz in external clock mode.
Choosing Power-Down Mode
You can save power by placing the converter in a low-
current shutdown state between conversions. Select full
power-down mode or fast power-down mode via bits 1
and 0 of the DIN control byte with SHDN high or floating
(Tables 1 and 5). In both software power-down modes,
the serial interface remains operational, but the ADC
does not convert. Pull SHDN low at any time to shut
down the converter completely. SHDN overrides bits 1
and 0 of the control byte.
Full power-down mode turns off all chip functions that
draw quiescent current, reducing supply current to 2A
(typ). Fast power-down mode turns off all circuitry
except the bandgap reference. With fast power-down
mode, the supply current is 30A. Power-up time can be
shortened to 5s in internal compensation mode.
Table 4 shows how the choice of reference-buffer com-
pensation and power-down mode affects both power-up
delay and maximum sample rate. In external compensa-
tion mode, power-up time is 20ms with a 4.7F compen-
sation capacitor when the capacitor is initially fully
discharged. From fast power-down, start-up time can be
eliminated by using low-leakage capacitors that do not
discharge more than 1/2LSB while shut down. In power-
down, leakage currents at VREF cause droop on the ref-
erence bypass capacitor. Figures 11a and 11b show
the various power-down sequences in both external and
internal clock modes.
Software Power-Down
Software power-down is activated using bits PD1 and PD0
of the control byte. As shown in Table 5, PD1 and PD0
also specify the clock mode. When software shutdown is
asserted, the ADC operates in the last specified clock
mode until the conversion is complete. Then the ADC
powers down into a low quiescent-current state. In internal
clock mode, the interface remains active and conversion
results may be clocked out after the MAX1246/MAX1247
enter a software power-down.
The first logical 1 on DIN is interpreted as a start bit
and powers up the MAX1246/MAX1247. Following
the start bit, the data input word or control byte also
REFERENCE
BUFFER
REFERENCE-
BUFFER
COMPENSATION
MODE
VREF
CAPACITOR
(F)
POWER-DOWN
MODE
POWER-UP
DELAY
(s)
MAXIMUM
SAMPLING RATE
(ksps)
Enabled
Internal
Fast
5
26
Enabled
Internal
Full
300
26
Enabled
External
4.7
Fast
See Figure 13c
133
Enabled
External
4.7
Full
See Figure 13c
133
Disabled
Fast
2
133
Disabled
Full
2
133
Table 4. Typical Power-Up Delay Times
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