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参数资料
| 型号： | MAX1247BMJE |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | ADC |
| 英文描述： | +2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16 |
| 中文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP16 |
| 封装： | CERDIP-16 |
| 文件页数： | 5/24页 |
| 文件大小： | 223K |
| 代理商： | MAX1247BMJE |
M
+2.7V, Low-Power, 4-Channel,
S erial 12-Bit ADCs in QS OP-16
_______________________________________________________________________________________
5
Figure 1
MAX124_ _M
__________________________________________Typic al Operating Charac teristic s
(V
DD
= 3.0V, VREF = 2.500V, f
SCLK
= 2.0MHz, C
LOAD
= 20pF, T
A
= +25°C, unless otherwise noted.)
0.5
0
1024
2048
CODE
3072
4096
INTEGRAL NONLINEARITY
vs. CODE
0.3
-0.3
-0.5
-0.1
0.1
0.4
0.2
-0.4
-0.2
0
M
I
0.50
0.00
2.25
2.75
4.25
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
V
DD
(V)
I
3.75
5.25
3.25
4.75
M
MAX1246
MAX1247
0.00
0.10
0.20
0.30
0.40
0.50
0.05
0.15
0.25
0.35
0.45
-60
-20
20
60
100
140
INTEGRAL NONLINEARITY
vs. TEMPERATURE
TEMPERATURE
(°C)
I
M
MAX1247
MAX1246
V
DD
= 2.7V
TIMING CHARACTERISTICS
(V
DD
= +2.7V to +3.6V (MAX1246); V
DD
= +2.7V to +5.25V (MAX1247); T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
SYMBOL
PARAMETER
Note 1:
Tested at V
DD
= 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:
MAX1246—internal reference, offset nulled; MAX1247—external reference (VREF = +2.500V), offset nulled.
Note 4:
Ground “on” channel; sine wave applied to all “off” channels.
Note 5:
Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:
The common-mode range for the analog inputs is from AGND to V
DD
.
Note 7:
Guaranteed by design. Not subject to production testing.
Note 8:
External load should not change during conversion for specified accuracy.
Note 9:
ADC performance is limited by the converter’s noise floor, typically 300μVp-p.
Note
10:
Measured as
|
V
FS
(2.7V) - V
FS
(V
DD, MAX
)
|
.
Internal clock mode only (Note 7)
External clock mode only, Figure 2
External clock mode only, Figure 1
DIN to SCLK Setup
DIN to SCLK Hold
Figure 1
Figure 2
Figure 1
MAX124_ _C/E
CONDITIONS
ns
20
240
240
Figure 1
ns
ns
t
CSH
t
CH
ns
ns
240
t
STR
t
SCK
CS
Rise to SSTRB Output Disable
SSTRB Rise to SCLK Rise
ns
240
t
SDV
CS
Fall to SSTRB Output Enable
240
t
SSTRB
SCLK Fall to SSTRB
200
t
CL
SCLK Pulse Width Low
ns
200
SCLK Pulse Width High
ns
0
CS
to SCLK Rise Hold
ns
100
t
CSS
CS
to SCLK Rise Setup
ns
240
t
TR
CS
Rise to Output Disable
ns
t
DV
CS
Fall to Output Enable
20
200
t
DO
SCLK Fall to Output Data Valid
ns
0
t
DH
μs
ns
1.5
100
t
ACQ
t
DS
Acquisition Time
0
UNITS
MIN
TYP
MAX
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