参数资料
| 型号： | MAX1271BEAI+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 5/20页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 8CH 28-SSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 46 |
| 类型： | 数据采集系统（DAS），ADC |
| 分辨率（位）： | 12 b |
| 采样率（每秒）： | 110k |
| 数据接口： | 串行 |
| 电压电源： | 单电源 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 管件 |
| 产品目录页面： | 1396 (CN2011-ZH PDF) |
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________________________________
13
Internal Clock Mode (PD1 = 0, PD0 = 0)
In internal clock mode, the MAX1270/MAX1271 gener-
ate their conversion clock internally. This frees the
microprocessor from the burden of running the acquisi-
tion and the SAR conversion clock, and allows the con-
version results to be read back at the processor’s
convenience, at any clock rate from 0 to typically
10MHz.
SSTRB goes low after the falling edge of the last bit
(PD0) of the control byte has been shifted in, and
returns high when the conversion is complete.
Acquisition is completed and conversion begins on the
falling edge of the 4th internal clock pulse after the con-
trol byte; conversion ends on the falling edge of the
16th internal clock pulse (12 internal clock cycle pulses
are used for conversion). SSTRB will remain low for a
maximum of 15s, during which time SCLK should
remain low for best noise performance. An internal reg-
ister stores data while the conversion is in progress.
The MSB of the result byte (D11) is present at DOUT
starting at the falling edge of the last internal clock of
conversion. Successive falling edges of SCLK will shift
the remaining data out of this register (Figure 9).
Additional SCLK edges will result in zeros on DOUT.
When internal clock mode is selected, SSTRB does not
go into a high-impedance state when CS goes high.
Pulling CS high prevents data from being clocked in
and tri-states DOUT, but does not adversely affect a
tSDV
tSSTRB
SCLK 12
tSTR
SSTRB
SCLK
CS
tSSTRB
HIGH-Z
Figure 7. External Clock Mode—SSTRB Detailed Timing
CS
SCLK
DIN
DOUT
A/D STATE
13
19
24
26
31
32
14
16
37
START SEL2 SEL1 SEL0
BIP
RNG
PD1 PD0
D11 D10
D9
D7
D8
D6
D5
D4
D2
D3
D1
D0
LSB
8
1
MSB
LSB
MSB
START SEL2 SEL1 SEL0
BIP
RNG
PD1 PD0
START SEL2
CONTROL BYTE 0
RESULT
CONTROL BYTE 1
CONTROL BYTE 2
18 SCLK
SSTRB
D10
D11
D9
D8
D6
D7
D5
RESULT 1
ACQUISITION
6 SCLK
CONVERSION
12 SCLK
ACQUISITION
6 SCLK
CONVERSION
12 SCLK
HIGH-Z
Figure 8. External Clock Mode—18 Clocks/Conversion Timing
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1271BEAI+ | 功能描述:模数转换器 - ADC 12-Bit 8Ch 110ksps 4.18V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1271BEAI+T | 功能描述:模数转换器 - ADC 12-Bit 8Ch 110ksps 4.18V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1271BEAI-T | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1271BENG | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1271BENG+ | 功能描述:模数转换器 - ADC 12-Bit 8Ch 110ksps 4.18V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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