参数资料
型号: MAX1280BEUP+T
厂商: Maxim Integrated Products
文件页数: 9/24页
文件大小: 0K
描述: IC ADC 12BIT 400KSPS 20-TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 12
采样率(每秒): 400k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 559mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 带卷 (TR)
输入数目和类型: 8 个单端,单极;8 个单端,双极;4 个伪差分,单极;4 个伪差分,双极
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
______________________________________________________________________________________
17
Table 4 details the four power modes with the corre-
sponding supply current and operating sections. For
data rates achievable in software power-down modes,
see Power-Down Sequencing section.
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down. Unlike software power-down mode, the
conversion is terminated immediately. When returning
to normal operation from SHDN with an external refer-
ence, the MAX1280/MAX1281 can be considered fully
powered-up within 2s of actively pulling SHDN high.
When using the internal reference, the conversion
should be initiated only after the reference has settled;
its recovery time depends on the external bypass
capacitors and shutdown duration.
Power-Down Sequencing
The MAX1280/MAX1281’s automatic power-down
modes can save considerable power when operating at
less than maximum sample rates. Figures 10 and 11
show the average supply current as a function of the
sampling rate.
Using Full Power-Down Mode
Full power-down mode (FULLPD) achieves the lowest
power consumption at up to 1000 conversions per
channel per second. Figure 10a shows the MAX1281’s
power consumption for 1- or 8-channel conversions
using full power-down mode (PD1 = PD0 = 0), with the
internal reference and the maximum clock speed. A
0.01F bypass capacitor plus the internal 17k
refer-
ence resistor at REFADJ forms an RC filter with a 200s
time constant. To achieve full 12-bit accuracy, 10 time
constants or 2ms are required after power-up if the
bypass capacitor is fully discharged between conver-
sions. Waiting this 2ms in FASTPD mode or reduced-
power mode (REDP) instead of full power-down mode
can further reduce power consumption. This is
achieved by using the sequence shown in Figure 12a.
Figure 10b shows the MAX1281’s power consumption
for 1- or 8-channel conversions using FULLPD mode
(PD1 = PD0 = 0), an external reference, and the maxi-
mum clock speed. One dummy conversion to power-up
the device is needed, but no wait-time is necessary to
start the second conversion, thereby achieving lower
power consumption at up to the full sampling rate.
Using Fast Power-Down and
Reduced-Power Modes
FASTPD and REDP modes achieve the lowest power
consumption at speeds close to the maximum sample
rate. Figure 11 shows the MAX1281’s power consump-
tion in FASTPD mode (PD1 = 0, PD0 = 1), REDP mode
(PD1 = 1, PD0 = 0), and (for comparison) normal
operating mode (PD1 = 1, PD0 = 1). The figure shows
0
0.50
0.25
1.00
0.75
1.25
1.50
0.0001
0.01
0.001
0.1
1
10
TIME IN SHUTDOWN (s)
REFERENCE
POWER-UP
DELAY
(ms)
MAX1281
VDD1 = VDD2 = 3.0V
CLOAD = 20pF
CODE = 101010000000
1000
100
10
1
0.1
10
1
100
1k
10k
SAMPLING RATE (sps)
SUPPLY
CURRENT
(
A)
8 CHANNELS
1 CHANNEL
10,000
1000
10
100
1
100
10
1k
10k
100k
SAMPLING RATE (sps)
SUPPLY
CURRENT
(
A)
MAX1281
VDD1 = VDD2 = 3.0V
CLOAD = 20pF
CODE = 101010000000
8 CHANNELS
1 CHANNEL
Figure 9. Reference Power-Up Delay vs. Time in Shutdown
Figure 10a. Average Supply Current vs. Sample Rate (Using
FULLPD and Internal Reference)
Figure 10b. Average Supply Current vs. Sampling Rate (Using
FULLPD and External Reference)
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