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参数资料
| 型号： | MAX1285BESA+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/15页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 300KSPS 8-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 位数： | 12 |
| 采样率（每秒）： | 300k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 2.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个单端，单极 |
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
_______________________________________________________________________________________
5
SCLK Rise to CS Fall Ignore
tCSO
35
ns
SCLK Rise to CS Rise Hold
tCSH
0
ns
CS Fall to SCLK Rise Setup
tCSS
35
ns
SCLK Pulse-Width Low
tCL
62
ns
CS Rise to SCLK Rise Ignore
tCS1
35
ns
SCLK Rise to DOUT Hold
tDOH
10
ns
SCLK Rise to DOUT Valid
tDOV
80
ns
CLOAD = 20pF
SCLK Pulse-Width High
tCH
62
ns
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
SCLK Period
tCP
156
ns
TIMING CHARACTERISTICS—MAX1284 (Figures 1, 2, 8, 9)
(VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.)
TIMING CHARACTERISTICS—MAX1285 (Figures 1, 2, 8, 9)
(VDD = +2.7V to +3.6V, TA = TMIN to TMAX, unless otherwise noted.)
Note 1: Tested at VDD = VDD(MIN).
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Internal reference, offset, and reference errors nulled.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA due to
production test limitations.
Note 6: Electrical characteristics are guaranteed from VDD(MIN) to VDD(MAX). For operations beyond this range, see Typical
Operating Characteristics.
Note 7: MAX1284 tested with 20pF on DOUT and fSCLK = 6.4MHz, 0 to 5V. MAX1285 tested with same loads, fSCLK = 4.8MHz,
0 to 3V. DOUT = full scale.
CS Rise to DOUT Disable
tDOD
10
65
ns
CS Fall to DOUT Enable
tDOE
65
ns
CS Pulse-Width High
tCSW
100
ns
CLOAD = 20pF
SCLK Rise to CS Fall Ignore
tCSO
45
ns
SCLK Rise to CS Rise Hold
tCSH
0
ns
CS Fall to SCLK Rise Setup
tCSS
45
ns
SCLK Pulse-Width Low
tCL
83
ns
CS Rise to SCLK Rise Ignore
tCS1
45
ns
SCLK Rise to DOUT Hold
tDOH
13
ns
SCLK Rise to DOUT Valid
tDOV
100
ns
CS Rise to DOUT Disable
tDOD
13
85
ns
CLOAD = 20pF
CS Fall to DOUT Enable
tDOE
85
ns
CS Pulse-Width High
tCSW
100
ns
CLOAD = 20pF
SCLK Period
tCP
208
SCLK Pulse-Width High
tCH
83
ns
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
ns
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