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参数资料
| 型号： | MAX1285BESA+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 5/15页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 300KSPS 8-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 位数： | 12 |
| 采样率（每秒）： | 300k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 2.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个单端，单极 |
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
______________________________________________________________________________________
13
Figure 14 shows the recommended system ground con-
nections. Establish a single-point analog ground (“star”
ground point) at GND, separate from the logic ground.
Connect all other analog grounds and DGND to this star
ground point for further noise reduction. No other digital
system ground should be connected to this single-point
analog ground. The ground return to the power supply for
this ground should be low impedance and as short as
possible for noise-free operation.
High-frequency noise in the VDD power supply may affect
the ADC’s high-speed comparator. Bypass this supply to
the single-point analog ground with 0.1F and 10F
bypass capacitors. Minimize capacitor lead lengths for
best supply noise rejection. To reduce the effects of sup-
ply noise, a 10
Ω resistor can be connected as a lowpass
filter to attenuate supply noise (Figure 14).
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1284/MAX1285 are mea-
sured using the endpoints method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A DNL
error specification of 1LSB or less guarantees no missing
codes and a monotonic transfer function.
CS
SCLK
DOUT
916
8
1
D0
D11
D10
D9
D8
D6
D5
D4
D3
D2
D1
D7
FIRST BYTE READ
SECOND BYTE READ
HIGH-Z
SCLK
DOUT
CS
14
13
D11
D10
D9
D8
D4
D5
D6
D3
D2
D1
D0
HIGH-Z
D7
HIGH-Z
Figure 12. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)
Figure 13. QSPI Serial Interface Timing (CPOL = 0, CPHA = 1)
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