参数资料
型号: MAX1292EVKIT
厂商: Maxim Integrated Products
文件页数: 19/20页
文件大小: 0K
描述: EVALUATION KIT FOR MAX1292
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
ADC 的数量: 1
位数: 12
采样率(每秒): 400k
数据接口: 并联
输入范围: ±VREF/2
在以下条件下的电源(标准): 9.5mW @ 400kSPS
工作温度: 0°C ~ 70°C
已用 IC / 零件: MAX1292,MAX1293
已供物品:
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
8
_______________________________________________________________________________________
Pin Description
NAME
FUNCTION
1
HBEN
High Byte Enable. Used to multiplex the 12-bit conversion result.
1: Four MSBs are multiplexed on the data bus.
0: Eight LSBs are available on the data bus.
PIN
2
D7
Three-State Digital I/O Line (D7)
3
D6
Three-State Digital I/O Line (D6)
4
D5
Three-State Digital I/O Line (D5)
5
D4
Three-State Digital I/O Line (D4)
6
D3/D11
Three-State Digital I/O Line (D3, HBEN = 0; D11, HBEN = 1)
7
D2/D10
Three-State Digital I/O Line (D2, HBEN = 0; D10, HBEN = 1)
8
D1/D9
Three-State Digital I/O Line (D1, HBEN = 0; D9, HBEN = 1)
9
D0/D8
Three-State Digital I/O Line (D0, HBEN = 0; D8, HBEN = 1)
10
INT
INT goes low when the conversion is complete and the output data is ready.
11
RD
Active-Low Read Select. If CS is low, a falling edge on RD enables the read operation on the
data bus.
12
WR
Active-Low Write Select. When CS is low in internal acquisition mode, a rising edge on WR
latches in configuration data and starts an acquisition plus a conversion cycle. When CS is
low in external acquisition mode, the first rising edge on WR ends acquisition and starts a
conversion.
13
CLK
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible
clock. In internal clock mode, connect this pin to either VDD or GND.
14
CS
Active-Low Chip Select. When CS is high, digital outputs (INT, D7–D0) are high impedance.
15
CH7
Analog Input Channel 7
16
CH6
Analog Input Channel 6
17
CH5
Analog Input Channel 5
18
CH4
Analog Input Channel 4
19
CH3
Analog Input Channel 3
20
CH2
Analog Input Channel 2
21
CH1
Analog Input Channel 1
22
CH0
Analog Input Channel 0
23
COM
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and
must be stable to ±0.5 LSB during conversion.
24
GND
Analog and Digital Ground
25
REFADJ
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a 0.01F
capacitor. When using an external reference, connect REFADJ to VDD to disable the internal
bandgap reference.
26
REF
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7F capacitor to GND
when using the internal reference.
27
VDD
Analog +5V Power Supply. Bypass with a 0.1F capacitor to GND.
28
VLOGIC
Digital Power Supply. VLOGIC powers the digital outputs of the data converter and can range
from +2.7V to VDD + 300mV.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MAX1290
MAX1292
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MAX1293ACEG+T 功能描述:模数转换器 - ADC 12-Bit 4Ch 250ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
MAX1293ACEG-T 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
MAX1293AEEG 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32