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| 型号： | MAX1294ACEI+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/19页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 420KSPS 28-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 50 |
| 位数： | 12 |
| 采样率（每秒）： | 420k |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 667mW |
| 电压电源： | 单电源 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 28-QSOP |
| 包装： | 管件 |
| 输入数目和类型： | 6 个单端，单极；6 个单端，双极；3 个伪差分，单极；3 个伪差分，双极 |
MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
4
_______________________________________________________________________________________
tTR
10
40
ns
CLOAD = 20pF, Figure 1
RD Rise to Output Disable
WR to CLK Fall Setup Time
tCWS
60
ns
CLK Pulse Width High
ns
CLK Period
tCH
40
RD Fall to Output Data Valid
tDO
10
50
ns
RD Fall to INT High Delay
tINT1
50
ns
CS Fall to Output Data Valid
tDO2
100
ns
CLOAD = 20pF, Figure 1
tCP
132
CLK Pulse Width Low
tCL
40
ns
Data Valid to WR Rise Time
tDS
40
ns
WR Rise to Data Valid Hold Time
tDH
0
ns
CLK Fall to WR Hold Time
tCWH
40
ns
CS to CLK or WR Setup Time
tCSWS
40
ns
CLK or WR to CS Hold Time
tCSWH
0
ns
CS Pulse Width
tCS
100
ns
WR Pulse Width (Note 8)
tWR
60
ns
tTC
10
60
ns
CLOAD = 20pF, Figure 1
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
CS Rise to Output Disable
Note 1: Tested at VDD = +5V, COM = GND, unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
TIMING CHARACTERISTICS
(VDD = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7F capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle),
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
3k
3k
DOUT
VDD
a) High-Z to VOH and VOL to VOH
b) High-Z to VOL and VOH to VOL
CLOAD
20pF
CLOAD
20pF
Figure 1. Load Circuits for Enable/Disable Times
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1294ACEI+ | 功能描述:模数转换器 - ADC 12-Bit 6Ch 420ksps 5.5V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1294ACEI+T | 功能描述:模数转换器 - ADC 12-Bit 6Ch 420ksps 5.5V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1294ACEI-T | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1294AEEI | 功能描述:模数转换器 - ADC Integrated Circuits (ICs) RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1294AEEI+ | 功能描述:模数转换器 - ADC 12-Bit 6Ch 420ksps 5.5V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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